CPU Design Verification Engineer
Description For CPU Design Verification Engineer
Google is seeking a CPU Design Verification Engineer to join their Server Chip Design team. As part of Google's Technical Infrastructure team, you'll be responsible for verifying complex digital designs and collaborating with design and verification engineers on active projects. Your role will involve the full lifecycle of verification, from planning to test execution and coverage closure.
At Google, we face unique computational challenges that require custom hardware solutions. As a Hardware Engineer, you'll be at the forefront of designing and building the systems that power Google's vast computing infrastructure. Your work will directly impact millions of Google users by shaping the machinery in our cutting-edge data centers.
Key responsibilities include:
- Planning verification of digital design blocks
- Creating and enhancing random verification environments using SystemVerilog and UVM
- Identifying and writing coverage measures for stimulus and corner-cases
- Debugging tests with design engineers
- Providing coverage measures to track progress towards tape-out
The ideal candidate will have a strong background in Electrical Engineering or Computer Science, with experience in digital logic verification, SystemVerilog, and standard IP components. You'll be working with state-of-the-art technology and contributing to the architecture that keeps Google's networks running smoothly.
Join us in building the next generation of Google platforms and help shape the future of technology. If you're passionate about solving complex problems, pushing the boundaries of hardware design, and working with a team of talented engineers, this role offers an exciting opportunity to make a significant impact in the world of technology.
Responsibilities For CPU Design Verification Engineer
- Plan the verification of digital design blocks by understanding the design specification and interact with design engineers to identify important verification scenarios
- Create and enhance random verification environments using SystemVerilog and Universal Verification Methodology (UVM), or formally verify designs with System Verilog Assertions (SVA) and industry leading formal tools
- Identify and write all types of coverage measures for stimulus and corner-cases
- Debug tests with design engineers to deliver functionally correct design blocks
- Provide close coverage measures to identify verification holes and to show progress towards tape-out
Requirements For CPU Design Verification Engineer
- Bachelor's degree in Electrical Engineering or equivalent practical experience
- 3 years of experience creating and using verification components and environments in standard verification methodology
- Experience verifying digital logic at Register-Transfer Level (RTL) level using SystemVerilog or Specman/E for Field Programmable Gate Arrays or Application-Specific Integrated Circuits (ASIC)
- Experience verifying digital systems using standard IP components/interconnects (e.g., microprocessor cores etc.)
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