CPU Design Verification Engineer

Google is a global technology company that develops custom silicon solutions and powers direct-to-consumer products used by millions worldwide.
Embedded
Mid-Level Software Engineer
In-Person
5,000+ Employees
3+ years of experience
Enterprise SaaS

Description For CPU Design Verification Engineer

Google's Technical Infrastructure team is seeking a CPU Design Verification Engineer to join their server chip design team. This role is crucial in developing custom silicon solutions that power Google's direct-to-consumer products. As a CPU Design Verification Engineer, you'll be part of a diverse R&D team responsible for building verification components, implementing constrained-random testing, and ensuring verification closure.

You'll work closely with design and verification engineers, creating efficient verification environments that thoroughly test designs through various scenarios. The role involves managing the complete verification lifecycle, from planning to test execution and coverage closure. You'll be instrumental in ensuring the functionality and reliability of digital designs that form the backbone of Google's infrastructure.

The position offers the opportunity to work with cutting-edge technology in Google's data centers and contribute to the next generation of Google platforms. You'll be part of a team that takes pride in being "engineers' engineers" and maintains the networks that provide users with the best possible experience. The role requires expertise in SystemVerilog/UVM or Specman, with opportunities to work on complex verification challenges.

This is an excellent opportunity for someone with a strong background in electrical engineering and digital logic verification who wants to impact products used by millions worldwide. You'll be working in either Tel Aviv or Haifa, Israel, contributing to Google's mission of developing innovative hardware solutions with unparalleled performance and efficiency.

Last updated 4 days ago

Responsibilities For CPU Design Verification Engineer

  • Plan the verification of digital design blocks by understanding design specification and identifying important verification scenarios
  • Create and enhance constrained-random verification environments using SystemVerilog/UVM, or Specman
  • Identify and write all types of coverage measures for stimulus and corner-cases
  • Debug tests with design engineers to deliver functionally correct design blocks
  • Lead coverage measures to identify verification holes and show progress towards tape-out

Requirements For CPU Design Verification Engineer

Python
  • Bachelor's degree in Electrical Engineering or equivalent practical experience
  • 3 years of experience verifying digital logic at RTL level using SystemVerilog, or Specman/E for FPGAs or ASICs
  • Experience verifying digital systems using standard IP components/interconnects
  • Experience creating and using verification components and environments in standard verification methodology

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