CPU Register Transfer Level Design Engineer, Silicon
Description For CPU Register Transfer Level Design Engineer, Silicon
Google is seeking a CPU Register Transfer Level Design Engineer to join their diverse team focused on developing custom silicon solutions for Google's direct-to-consumer products. This role involves working on cutting-edge CPU front-end designs and micro-architecture for next-generation processors. The position offers competitive compensation ($127,000-$187,000) plus bonus, equity, and comprehensive benefits.
The ideal candidate will have strong experience in digital logic design principles, RTL design concepts, and programming languages like Verilog or SystemVerilog. They will be responsible for proposing and implementing performance-enhancing micro-architecture features, optimizing designs for power and efficiency, and working closely with architects and performance teams.
This is an exciting opportunity to contribute to Google's hardware innovation, directly impacting products used by millions worldwide. The role combines technical expertise in CPU design with collaborative teamwork, requiring both strong engineering skills and effective communication abilities. The position offers professional growth in a cutting-edge technology environment, working with state-of-the-art processor design techniques and methodologies.
The role is based in several possible locations including Mountain View, Austin, Portland, or Poughkeepsie, offering flexibility in work location while being part of Google's mission to organize the world's information and make it universally accessible. This position is perfect for someone passionate about processor design, interested in pushing the boundaries of hardware performance, and eager to contribute to next-generation computing solutions.
Responsibilities For CPU Register Transfer Level Design Engineer, Silicon
- Contribute to Central Processing Unit (CPU) front-end designs, emphasizing micro-architecture and Register Transfer Level (RTL) design for the next generation CPU
- Propose performance enhancing micro-architecture features with efficiency. Work with architects and performance teams for trade-off studies
- Deliver designs meet Power, Performance and Area (PPA) goals with production quality
- Be familiar with techniques for at least one processor functional block. Interpret the techniques into design constructs and languages
- Communicate pros and cons of micro-architecture enhancements and facilitate final decision making
Requirements For CPU Register Transfer Level Design Engineer, Silicon
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience
- 3 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog
- Experience with logic synthesis techniques to optimize RTL code, performance and power as well as low-power design techniques
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture (preferred)
Benefits For CPU Register Transfer Level Design Engineer, Silicon
- Base salary
- Bonus
- Equity
- Benefits package
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