CPU Register Transfer Level Design Engineer, Silicon
Description For CPU Register Transfer Level Design Engineer, Silicon
Google is seeking a CPU Register Transfer Level Design Engineer to join their hardware team, focusing on developing custom silicon solutions for Google's direct-to-consumer products. This role combines cutting-edge technology with practical implementation, requiring expertise in digital logic design and RTL concepts.
The position offers an opportunity to work on next-generation CPU architectures, emphasizing micro-architecture and RTL design. You'll be part of a diverse team that pushes boundaries and develops solutions that power Google's future hardware experiences. The role involves collaborating with architects and performance teams to optimize designs for power, performance, and area goals.
As a CPU RTL Design Engineer, you'll contribute to front-end designs, propose performance-enhancing features, and work on processor functional blocks. The position requires strong technical skills in digital logic design, RTL concepts, and experience with languages like Verilog or SystemVerilog. You'll also need to effectively communicate technical decisions and trade-offs.
The role offers competitive compensation, including a base salary range of $127,000-$187,000, plus bonus, equity, and comprehensive benefits. You'll be working at one of Google's main tech hubs, contributing to products used by millions worldwide. This is an excellent opportunity for someone passionate about hardware design and looking to make a significant impact on Google's future hardware products.
The ideal candidate will have at least 3 years of relevant experience and a strong educational background in Electrical Engineering, Computer Engineering, or Computer Science. You'll be joining a company known for its innovative culture and commitment to developing radically helpful experiences through the combination of AI, software, and hardware technologies.
Responsibilities For CPU Register Transfer Level Design Engineer, Silicon
- Contribute to Central Processing Unit (CPU) front-end designs, emphasizing micro-architecture and Register Transfer Level (RTL) design for the next generation CPU
- Propose performance enhancing micro-architecture features with efficiency. Work with architects and performance teams for trade-off studies
- Deliver designs meet Power, Performance and Area (PPA) goals with production quality
- Be familiar with techniques for at least one processor functional block. Interpret the techniques into design constructs and languages in order to provide guidance to and participate in the performance modeling effort
- Communicate pros and cons of micro-architecture enhancements and facilitate final decision making
Requirements For CPU Register Transfer Level Design Engineer, Silicon
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience
- 3 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog
- Experience with logic synthesis techniques to optimize RTL code, performance and power as well as low-power design techniques
Benefits For CPU Register Transfer Level Design Engineer, Silicon
- bonus
- equity
- benefits
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