Design Verification Engineer

Google organizes the world's information and makes it universally accessible and useful through innovative technology solutions.
$113,000 - $161,000
Embedded
Entry-Level Software Engineer
In-Person
5,000+ Employees
Consumer

Description For Design Verification Engineer

Google is seeking a Design Verification Engineer to join their Devices & Services team, focusing on developing custom silicon solutions for Google's direct-to-consumer products. This role combines cutting-edge hardware verification with Google's mission to organize world information. The position involves working with advanced verification methodologies like UVM and SystemVerilog to ensure the quality and reliability of digital design blocks.

The role is part of Google's broader initiative to create radically helpful experiences for users through the combination of AI, Software, and Hardware. You'll be contributing to the development of next-generation hardware experiences that deliver unparalleled performance, efficiency, and integration. The team researches, designs, and develops new technologies to make user interactions with computing faster, seamless, and more powerful.

As a Design Verification Engineer, you'll collaborate closely with design engineers, plan verification strategies, create test environments, and ensure comprehensive coverage of design specifications. The position offers competitive compensation including base salary, bonus, equity, and comprehensive benefits. This is an excellent opportunity for someone passionate about hardware verification and interested in working on products that impact millions of users worldwide.

The ideal candidate should have a strong background in electrical engineering or computer science, experience with verification methodologies, and the ability to work effectively in a collaborative environment. You'll be part of a team that pushes boundaries and innovates in the hardware space, making significant contributions to Google's consumer products.

Last updated 12 hours ago

Responsibilities For Design Verification Engineer

  • Plan the verification of digital design blocks by understanding the design specification and interacting with design engineers to identify important verification scenarios
  • Create and enhance constrained-random verification environments using SystemVerilog and Universal Vefication Methodology (UVM) or formally verify designs with SystemVerilog Assertions (SVA) and formal tools
  • Identify and write all types of coverage measures for stimulus and corner-cases
  • Debug tests with design engineers to deliver design blocks
  • Resolve coverage measures to identify verification holes and show progress towards tape-out

Requirements For Design Verification Engineer

Java
  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience
  • Experience with verification methodologies and languages such as Universal Vefication Methodology (UVM) or SystemVerilog
  • Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture (preferred)
  • Experience in low-power design verification (preferred)
  • Experience developing and maintaining verification test-benches, test-cases, and test-environments (preferred)

Benefits For Design Verification Engineer

Medical Insurance
Dental Insurance
Vision Insurance
Parental Leave
401k
Equity
  • Comprehensive benefits package including medical, dental, and vision insurance
  • Parental leave
  • 401k
  • Bonus
  • Equity

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