Design Verification Engineer, Security, Silicon
Description For Design Verification Engineer, Security, Silicon
Google is seeking a Design Verification Engineer for their Security and Silicon team in Bengaluru, India. This mid-level role is part of a diverse team developing custom silicon solutions for Google's direct-to-consumer products. The ideal candidate will have a strong background in digital system verification, experience with UVM, and knowledge of security and crypto blocks.
Key responsibilities include:
- Planning verification of complex digital design blocks
- Creating and enhancing constrained-random verification environments
- Identifying and writing coverage measures
- Debugging tests with design engineers
- Participating in defining overall SoC verification strategies
The role requires a Bachelor's degree in a relevant field and at least 3 years of experience with UVM and digital system verification. Preferred qualifications include advanced degrees, experience with security blocks, performance verification, and power-aware simulations.
This position offers the opportunity to shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration for products used by millions worldwide. The successful candidate will contribute to Google's mission of organizing the world's information and making it universally accessible and useful through innovative hardware solutions.
Google is committed to diversity, equality, and creating a culture of belonging. They offer a comprehensive benefits package and encourage applicants from all backgrounds to apply.
Responsibilities For Design Verification Engineer, Security, Silicon
- Plan the verification of complex digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios
- Create and enhance constrained-random verification environments using System Verilog and Universal Verification Methodology (UVM) or formally verify designs with System Verilog Assertions (SVA) and industry leading formal tools
- Identify and write all types of coverage measures for stimulus and corner-cases
- Debug tests with design engineers to deliver functionally correct design blocks
- Participate with architecture, design teams, silicon validation, and software teams in defining the overall verification strategy of our SoCs
Requirements For Design Verification Engineer, Security, Silicon
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience
- 3 years of experience creating and using verification components and environments in UVM
- Experience verifying digital systems using standard IP components/interconnects (e.g., microprocessor cores, hierarchical memory subsystems)
- Experience with verification techniques (i.e., constrained-random simulation, formal property verification or static verification)
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