Display Defect Metrology Engineer

Google's Raxium display group develops revolutionary semiconductor materials display technology for AR and light-field display applications.
$147,000 - $216,000
Embedded
Mid-Level Software Engineer
In-Person
5,000+ Employees
5+ years of experience
AR/VR

Description For Display Defect Metrology Engineer

Google's Raxium display group is at the forefront of revolutionary semiconductor materials display technology, specifically focused on advancing AR and light-field display applications. As a Display Defect Metrology Engineer, you'll be working in a state-of-the-art compound semiconductor fab in Silicon Valley, playing a crucial role in developing and implementing cutting-edge metrology techniques for inline wafer-level defect detection.

The position requires a strong background in semiconductor wafer defect metrology, with at least 5 years of experience and expertise in machine learning applications for defect classification. You'll be working in a fully onsite capacity in Fremont, CA, primarily in wafer fabrication cleanroom environments. The role demands a unique combination of technical expertise, problem-solving abilities, and strong collaborative skills.

Your responsibilities will span from guiding the development of advanced metrology equipment to executing experiments for defect characterization and working closely with equipment vendors. You'll be instrumental in establishing robust quality control measures and leading problem resolution processes using data-driven approaches.

The compensation package is competitive, ranging from $147,000 to $216,000 base salary, plus bonus, equity, and comprehensive benefits. This is an excellent opportunity for someone passionate about pushing the boundaries of display technology while working with a team that has startup roots but benefits from Google's resources and stability.

The ideal candidate will have a Master's degree in a relevant field, strong Python programming skills, and the ability to thrive in a fast-paced manufacturing environment. You'll be joining a team that's focused on disrupting next-generation display markets, making this an exciting opportunity for those interested in being at the cutting edge of display technology innovation.

Last updated 13 days ago

Responsibilities For Display Defect Metrology Engineer

  • Guide development and implementation of advanced inline wafer defect metrology equipment and techniques
  • Develop and execute experiments to identify and characterize defect sources and formation mechanisms
  • Collaborate with equipment vendors to improve and optimize defect metrology tools
  • Establish and maintain control charts, sampling plans, calibration, and measurement system analysis
  • Direct problem resolution processes for quality excursions using data analytics and methodical problem-solving

Requirements For Display Defect Metrology Engineer

Python
  • Master's degree in Electrical Engineering, Materials Science, Physics, or a related field, or equivalent practical experience
  • 5 years of experience working with semiconductor wafer defect metrology tools
  • 1 year of experience in machine learning models to accelerate automatic defect classification
  • Experience and expertise in image-based defect detection, classification, and machine learning algorithms
  • Knowledge of failure analysis (FA) techniques
  • Proficiency in Python programming and statistical analysis tools
  • Ability to learn fast, work independently, and adapt in a fast-paced environment
  • Excellent communication and problem-solving skills

Benefits For Display Defect Metrology Engineer

Medical Insurance
Dental Insurance
Vision Insurance
  • bonus
  • equity
  • benefits package

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