Google's Raxium display group is at the forefront of revolutionary semiconductor materials display technology, specifically focused on advancing AR and light-field display applications. As a Display Defect Metrology Engineer, you'll be working in a state-of-the-art compound semiconductor fab in Silicon Valley, playing a crucial role in developing and implementing cutting-edge metrology techniques for inline wafer-level defect detection.
The position requires a strong background in semiconductor wafer defect metrology, with at least 5 years of experience and expertise in machine learning applications for defect classification. You'll be working in a fully onsite capacity in Fremont, CA, primarily in wafer fabrication cleanroom environments. The role demands a unique combination of technical expertise, problem-solving abilities, and strong collaborative skills.
Your responsibilities will span from guiding the development of advanced metrology equipment to executing experiments for defect characterization and working closely with equipment vendors. You'll be instrumental in establishing robust quality control measures and leading problem resolution processes using data-driven approaches.
The compensation package is competitive, ranging from $147,000 to $216,000 base salary, plus bonus, equity, and comprehensive benefits. This is an excellent opportunity for someone passionate about pushing the boundaries of display technology while working with a team that has startup roots but benefits from Google's resources and stability.
The ideal candidate will have a Master's degree in a relevant field, strong Python programming skills, and the ability to thrive in a fast-paced manufacturing environment. You'll be joining a team that's focused on disrupting next-generation display markets, making this an exciting opportunity for those interested in being at the cutting edge of display technology innovation.