Google's Raxium display group is at the forefront of revolutionary semiconductor materials display technology, specifically designed for augmented reality (AR) and light-field display applications. As a Display Wafer Fab Metrology Engineer, you'll be instrumental in driving metrology learning and techniques for next-generation display technology.
The role is based in Fremont, CA, and requires working in wafer fabrication cleanroom environments. You'll be responsible for scaling toolsets for volume production and conducting deep investigations into characterization tools to understand and screen displays. This position demands extensive collaboration with process, yield, integration, device, and epi engineering groups.
The ideal candidate should have a Master's degree in Electrical Engineering, Optics, Physics, or related field, with 5 years of experience in semiconductor metrology tools. You'll need expertise in statistical analysis, data interpretation, and root cause analysis. Experience with III-V compound semiconductor fabrication and failure analysis techniques is highly valued.
This opportunity offers a competitive compensation package ranging from $142,000 to $211,000, plus bonus, equity, and comprehensive benefits. You'll be joining a dynamic team with start-up roots and access to a state-of-the-art compound semiconductor fab in Silicon Valley.
The role involves developing and implementing best practices for metrology and measurement tool control, partnering with external suppliers, and driving continuous improvement in process control. You'll be at the forefront of developing novel wafer fab metrology techniques that will shape the future of display technology.
Working at Google's Raxium group means being part of a team that's disrupting next-generation display markets, bringing users closer to a natural linkage between digital and physical realms. The position offers the chance to work with cutting-edge technology while contributing to groundbreaking developments in AR and display technology.