Google is seeking a Front End CAD/EDA-Methodology Tool Development Engineer to join their Technical Infrastructure team. This role combines hardware expertise with software development, focusing on developing custom silicon solutions for Google's direct-to-consumer products.
The position requires a strong background in ASIC Chip Design and hardware electronic design automation tools, along with proficiency in Python/C++ programming. You'll work at the intersection of traditional hardware development and cutting-edge AI/ML techniques, partnering with the Google Deepmind team to revolutionize chip design methodology.
As a key member of the team, you'll lead complex technical projects from conception to completion, focusing on infrastructure for chip design. Your responsibilities will include developing internal software tools, performing technical evaluations, and driving improvements in the ASIC and SoC EDA flow. You'll have the opportunity to influence and standardize methodology across various functional areas, including Design, Verification, and Emulation.
The role offers the chance to work with state-of-the-art technology and contribute to products that impact millions of users globally. You'll be part of Google's Technical Infrastructure team, which is responsible for building and maintaining the architecture that powers Google's entire product portfolio. The team takes pride in being "engineers' engineers" and pushes boundaries in hardware development.
This position is ideal for someone who combines technical expertise with leadership abilities, as you'll be guiding technical evaluations, participating in design reviews, and engaging in strategic discussions. You'll work directly with hardware teams to prototype and deploy tools that improve Google's chip hardware development process.
The role offers the opportunity to work with cutting-edge technology, collaborate with world-class experts, and contribute to innovative solutions that power Google's next generation of hardware experiences. You'll be at the forefront of incorporating AI/ML techniques into chip design, working on projects that deliver unparalleled performance, efficiency, and integration.