Full Chip CAD Physical Design Verification Engineer
Description For Full Chip CAD Physical Design Verification Engineer
Google is seeking a Full Chip CAD Physical Design Verification Engineer to join their Technical Infrastructure team. This role involves developing custom silicon solutions for Google's direct-to-consumer products, pushing boundaries in hardware innovation. The ideal candidate will have expertise in Electronic Design Automation (EDA) tools, RTL2GDS flows, and advanced node design techniques. They will work on implementing complex system-on-chips, applying floorplanning and power grid design methodologies, and utilizing tools like Cadence and Synopsis. The position requires a strong background in electrical engineering or computer science, with experience in the semiconductor/EDA industry. This role offers the opportunity to shape the next generation of Google's hardware experiences, delivering unparalleled performance, efficiency, and integration. The work environment emphasizes diversity, innovation, and the development of cutting-edge technology that powers Google's vast product portfolio.
Responsibilities For Full Chip CAD Physical Design Verification Engineer
- Implement large, complex system-on-chips (SoCs), subsystems, and sub-wrappers
- Demonstrate understanding of issues and solutions associated with implementing complex SoCs
- Apply floorplanning, power grid design, and place-and-route methodologies
- Utilize advanced node design techniques and optimization
- Develop scripts using Synopsis TCL and Python
Requirements For Full Chip CAD Physical Design Verification Engineer
- Bachelor's degree in Electrical Engineering, Computer Science, or a related field
- Experience in Electronic Design Automation (EDA) tools and RTL2GDS flows
- Experience in the semiconductor/EDA industry
- Understanding of the Register-Transfer Level (RTL)-to-Graphic Data Stream (GDS)II flow
- Experience in using Cadence design tools
- Knowledge of floorplanning, power grid design, and place-and-route methodologies
- Expertise in using Synopsis tools like Floorplan Compiler (FC) and formality
- Understanding of advanced node design (e.g., 5nm and below) and related optimization techniques
- Scripting skills in Synopsis TCL, with expertise in Python
Benefits For Full Chip CAD Physical Design Verification Engineer
- Equal opportunity employer
- Affirmative action employer
- Inclusive work environment
- Accommodation for applicants with special needs
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