Full Chip CAD Physical Design Verification Engineer

Google is seeking a Full Chip CAD Physical Design Verification Engineer to join their Technical Infrastructure team. This role is crucial in developing custom silicon solutions that power Google's direct-to-consumer products. The position involves working with cutting-edge technology in chip design and verification, utilizing advanced EDA tools and methodologies.

The ideal candidate will be part of a diverse team that pushes boundaries in hardware development, working on projects that impact millions of users worldwide. You'll be responsible for implementing complex system-on-chips, managing RTL-to-GDSII flows, and utilizing advanced node design techniques for 5nm and below technologies.

This role offers the opportunity to work at one of the world's leading technology companies, contributing to the architecture that powers Google's vast product portfolio. You'll be working with state-of-the-art tools and technologies, including Cadence design tools and Synopsis tools, while applying your expertise in Python and TCL scripting.

The position requires a strong background in electrical engineering or computer science, with experience in semiconductor/EDA industry. You'll be working on challenging projects that require expertise in floorplanning, power grid design, and place-and-route methodologies. This is an excellent opportunity for someone who wants to make a significant impact on the future of Google's hardware experiences, focusing on performance, efficiency, and integration.

Google offers a collaborative work environment, emphasizing diversity and inclusion, and provides the chance to work on cutting-edge technology that shapes the future of computing. The role is based in either Tel Aviv or Haifa, Israel, offering the opportunity to work with global teams while contributing to Google's next generation of hardware platforms.