Google is seeking a Principal Interposer Physical Design Engineer to join their Technical Infrastructure team. This role is crucial in developing custom silicon solutions that power Google's direct-to-consumer products. The position requires extensive experience in ASIC physical design and advanced process nodes, with a focus on interposer routing for 2.5D and 3D packaging.
The ideal candidate will have a strong background in electrical engineering or related fields, with 10+ years of experience in ASIC physical design flows. They will be responsible for complex technical tasks including interposer routing, high-speed interface connections, and ASIC top-level I/O planning. The role involves collaboration with various design teams and requires expertise in layout, physical verification, and power integrity analysis.
Working at Google's Technical Infrastructure team means being part of the backbone that keeps Google's vast product portfolio running smoothly. The team is responsible for developing and maintaining data centers and building next-generation Google platforms. They take pride in being the "engineers' engineers" and are committed to providing the best possible user experience through their technical innovations.
The position offers a competitive compensation package, including a base salary range of $177,000-$266,000, plus bonus, equity, and comprehensive benefits. This is an opportunity to work on cutting-edge technology that impacts millions of users worldwide, while being part of a diverse team that pushes boundaries and drives innovation in hardware experiences.
The role requires strong technical expertise combined with collaborative skills, as you'll be working closely with ASIC designers, package designers, and system architects. You'll be involved in making critical technical evaluations and recommendations that will shape the future of Google's hardware infrastructure. The position is based in the San Francisco Bay Area, offering the chance to work in one of the world's leading tech hubs.