Layout CAD Engineer, Silicon

Google organizes the world's information and creates innovative AI, software, and hardware solutions.
Backend
Mid-Level Software Engineer
In-Person
5,000+ Employees
5+ years of experience
AI · Consumer · Hardware

Description For Layout CAD Engineer, Silicon

Google is seeking a Layout CAD Engineer to join their diverse team focused on developing custom silicon solutions for Google's direct-to-consumer products. This role combines Google's expertise in AI, Software, and Hardware to create innovative experiences. The position involves working on semiconductor layout flow development and automation, requiring strong technical skills in physical design tools and memory compiler software development. The ideal candidate will have extensive experience in layout verification and integration, contributing to products that impact millions of users worldwide. The role offers the opportunity to shape next-generation hardware experiences, focusing on performance, efficiency, and integration. As part of Google's mission to organize world's information, you'll work with cutting-edge technology while collaborating with layout engineers to ensure design robustness and develop critical verification systems. This position represents a unique opportunity to contribute to Google's hardware innovation while working with state-of-the-art tools and technologies in semiconductor design.

Last updated a day ago

Responsibilities For Layout CAD Engineer, Silicon

  • Collaborate with layout engineers to identify critical checks that ensure correctness and robustness of standard-cells and memory arrays
  • Architect and drive the development of checkers to identify patterning and abutment issues in the design
  • Drive the development of a memory compiler
  • Streamline existing workflows and create new ones based on project requirements

Requirements For Layout CAD Engineer, Silicon

Python
  • Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience
  • 5 years of experience in semiconductor layout flow development and automation
  • Experience in Scripting languages such as Python or TCL
  • Master's degree in Electrical Engineering, Computer Science or equivalent industry experience (preferred)
  • Experience in using physical design tools such as place and route tools, and layout verification tools (preferred)
  • Experience in developing memory compiler software (preferred)
  • Knowledge of LEF collateral verification, Caliber tool Suite and standard-cell layout (preferred)
  • Knowledge of layout integration challenges (preferred)

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