Layout Design Engineer, Silicon

Google is seeking a Layout Design Engineer to join their diverse team focused on developing custom silicon solutions for direct-to-consumer products. This role is crucial in shaping the next generation of hardware experiences at Google, working on high-performance memory and circuit design.

The position requires extensive experience in VLSI design, specifically in layout design for high-speed/low power memories and verification activities. You'll be working with cutting-edge 3nm technology nodes, developing memory arrays and standard cells that power Google's innovative products.

As a Layout Design Engineer, you'll collaborate with various teams, including Physical Design and Compute IP teams, to create efficient and powerful solutions. Your responsibilities will range from analyzing design specifications and running simulations to optimizing Performance, Power, and Area (PPA) of memory arrays.

The ideal candidate should have a strong background in VLSI or Computer Engineering, with at least 5 years of hands-on experience in memory layout design. Knowledge of tools like Virtuoso XL and understanding of FinFET technology nodes is essential.

This role offers the opportunity to work on technology that impacts millions of users worldwide, combining the best of Google's AI, Software, and Hardware capabilities. You'll be part of a team that pushes boundaries and innovates in the silicon design space, contributing to Google's mission of organizing the world's information and making it universally accessible.