Layout Design Engineer, Silicon

Google is seeking a Layout Design Engineer to join their diverse team focused on developing custom silicon solutions for direct-to-consumer products. This role is crucial in shaping the next generation of hardware experiences at Google, working on technologies that power products used by millions worldwide.

The position requires deep expertise in VLSI and computer engineering, with a strong focus on memory array layout and verification. You'll be working with cutting-edge 3nm technology nodes, designing and optimizing high-speed/low power memories. The role involves complex technical work including schematic design, layout extraction, and spice simulations.

As a Layout Design Engineer, you'll collaborate with various teams to improve Performance, Power, and Area (PPA) of memory arrays and standard-cells. You'll be involved in everything from analyzing design specifications to ensuring seamless integration with the Physical Design team. The position offers the opportunity to work with state-of-the-art tools like Virtuoso XL and Star-RC/QFS.

This is an excellent opportunity for someone passionate about hardware design who wants to make a direct impact on Google's consumer products. You'll be part of Google's mission to organize the world's information and make it universally accessible, working at the intersection of AI, software, and hardware to create radically helpful experiences.

The role offers the chance to work in a diverse, inclusive environment where innovation is encouraged. Google is committed to creating a culture of belonging and provides equal employment opportunities. The position is based in Bengaluru, India, where you'll be part of a team pushing the boundaries of what's possible in hardware design.