Lead CPU RTL Front End Design Engineer, Subsystem
Description For Lead CPU RTL Front End Design Engineer, Subsystem
Google is seeking a Lead CPU RTL Front End Design Engineer to join their hardware team, focusing on developing custom silicon solutions that power Google's direct-to-consumer products. This role offers an opportunity to shape the next generation of hardware experiences, working on cutting-edge CPU subsystem development and microarchitecture design.
The position requires a deep understanding of digital logic design principles and RTL design concepts, with extensive experience in languages like Verilog or SystemVerilog. The ideal candidate will have 10+ years of experience and strong expertise in logic synthesis techniques for optimizing RTL code, performance, and power consumption.
As a Lead Engineer, you'll work closely with various teams including Verification, Physical Design, Software, and Architecture teams to deliver high-quality designs that meet performance, power, and area goals. The role involves both technical leadership and hands-on development, requiring excellent communication skills to articulate complex technical decisions and trade-offs.
The compensation package is highly competitive, ranging from $227,000 to $320,000 base salary, plus bonus, equity, and comprehensive benefits. Google offers multiple location options including Mountain View, Austin, Portland, and Poughkeepsie, providing flexibility for candidates.
This is an excellent opportunity for experienced engineers who want to work on innovative hardware solutions at scale, contributing to products used by millions of people worldwide. The role combines technical expertise with leadership responsibilities, making it ideal for those looking to make a significant impact in hardware development at one of the world's leading technology companies.
Responsibilities For Lead CPU RTL Front End Design Engineer, Subsystem
- Participate in developing CPU subsystem. Develop CPU subsystem front-end designs, emphasizing on microarchitecture and RTL design for the next generation CPU
- Communicate the pros and cons of microarchitecture enhancements. Deliver designs, meeting PPA goals with production quality
- Work with the Verification team to ensure production of quality designs, and the physical design and power teams to meet frequency, power, and area goals
- Become familiar with modern techniques, interpret the techniques into design constructs and languages in order to provide guidance to and participate in the performance evaluation effort
- Propose performance enhancing microarchitecture features, and work with Software, Architect, and Performance teams for trade-off studies
Requirements For Lead CPU RTL Front End Design Engineer, Subsystem
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience
- 10 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog
- Experience with logic synthesis techniques to optimize RTL code, performance and power as well as low-power design techniques
- Experience with RTL language (System Verilog) and related design processes (e.g., Lint, UPF)
Benefits For Lead CPU RTL Front End Design Engineer, Subsystem
- Comprehensive medical, dental, and vision insurance
- 401k plan
- Equity compensation
- Bonus compensation
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