Microarchitecture RTL Lead, Silicon AI/ML, TPU, Google Cloud
Description For Microarchitecture RTL Lead, Silicon AI/ML, TPU, Google Cloud
Google is seeking a Microarchitecture RTL Lead for their Silicon AI/ML TPU team within Google Cloud. This role is at the forefront of AI/ML hardware acceleration, focusing on developing cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. The position involves leading a team in Bengaluru, developing custom silicon solutions for Google's TPU infrastructure.
The role combines technical leadership with hands-on development, requiring expertise in ASIC development, micro-architecture design, and team management. You'll be working on sophisticated AI/ML compute-intensive IPs and subsystems, collaborating with various teams including Architecture, Firmware, and Software to drive innovation in machine learning computation for data centers.
As a leader in this position, you'll be responsible for driving technical excellence in RTL implementation, design methodology, and system optimization. The role requires a strong background in ASIC/SoC design, verification, and testing, with particular emphasis on machine learning IP design and low precision/mixed precision numerics.
This is an opportunity to shape the future of AI hardware at Google, working with state-of-the-art technology that powers millions of users worldwide. You'll be part of Google's Technical Infrastructure team, which is fundamental to maintaining and advancing Google's vast product portfolio. The role offers the chance to work on challenging technical problems while leading and developing a team of talented engineers.
The ideal candidate will bring together technical expertise in hardware design, leadership capabilities, and a passion for AI/ML technology. This position offers the opportunity to make significant contributions to Google's AI infrastructure while working with cutting-edge technology in a collaborative, innovative environment.
Responsibilities For Microarchitecture RTL Lead, Silicon AI/ML, TPU, Google Cloud
- Lead a team of engineers in the Bengaluru design organization to deliver AI/ML compute intensive IPs and subsystems
- Work with Architecture, Firmware, and Software teams to drive feature closure and develop microarchitecture specifications
- Take ownership of one or more complex IPs or subsystems and implement RTL
- Drive design methodology, libraries, debug, code review in coordination with other IPs Design Verification (DV) teams and physical design teams
- Identify and drive power, performance, and area improvements for the domains owned
Requirements For Microarchitecture RTL Lead, Silicon AI/ML, TPU, Google Cloud
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience
- 8 years of experience in ASIC development with Verilog/SystemVerilog, VHDL, or Chisel
- 4 years of experience in people management, developing employees
- Experience in micro-architecture and design of Machine Learning IPs or Graphics IPs, handling Low Precision/Mixed Precision Numerics
- Experience in ASIC/SoC design verification, synthesis, timing/power analysis, and Design for Testing (DFT)
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