Network Register Transfer Level Design Engineer
Description For Network Register Transfer Level Design Engineer
Join Google's Technical Infrastructure team as a Network Register Transfer Level Design Engineer, where you'll be at the forefront of developing custom silicon solutions that power Google's data center infrastructure. This role combines hardware architecture and networking expertise, focusing on developing Application-Specific Integrated Circuits (ASICs) to accelerate networking in data centers.
You'll be part of a diverse team that pushes boundaries in hardware innovation, working on projects from specification to production. The position requires deep knowledge of networking protocols, RDMA-based transports, and system design principles for low latency and high throughput systems.
As a key member of the team, you'll contribute to Google's data center networking roadmap, participating in everything from architecture evaluation to implementation. You'll work with cutting-edge technologies, collaborating with software teams to optimize hardware/software interfaces and develop new layer protocols for data center networking.
The role offers the opportunity to shape the future of Google's technical infrastructure, working with state-of-the-art ASIC designs and networking technologies. You'll be part of the team that keeps Google's networks running efficiently, ensuring millions of users worldwide have the best possible experience.
This position is perfect for someone who combines deep technical expertise in hardware design with a passion for networking and system architecture. You'll be working in a collaborative environment, interfacing with multiple teams and contributing to projects that directly impact Google's infrastructure capabilities.
Responsibilities For Network Register Transfer Level Design Engineer
- Participate in evaluation of future ASIC designs and architecture for Google's data center networking roadmap
- Collaborate in developing new layer protocols for data center networking
- Understand interactions with software and other ASIC subsystems to implement data center networks
- Define performance hardware/software interfaces
- Write micro-architecture and design specifications
- Define efficient micro-architecture and block partitioning/interfaces and flows
Requirements For Network Register Transfer Level Design Engineer
- Bachelor's degree or equivalent practical experience
- 8 years of experience architecting networking ASICs from specification to production
- Experience working with design networking like RDMA and packet processing
- Experience developing Register Transfer Level (RTL) for ASIC subsystems
- Experience in Cross-functional, micro-architecture, design, verification, logic synthesis, and timing closure
- Experience in TCP, IP, Ethernet, PCIE and DRAM, Network on Chip principles and protocols
- Experience in estimating performance by analysis, modeling, and network simulation
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