Google's ML, Systems & Cloud AI (MSCA) organization is seeking a Networking RTL Design Engineer to join their team developing cutting-edge ASICs for data center networking acceleration. This role combines hardware expertise with networking knowledge, focusing on developing custom silicon solutions that power Google's infrastructure.
The position requires deep expertise in ASIC architecture, RDMA-based transports, and networking protocols. You'll be working on next-generation data center accelerators, participating in everything from initial specification to production implementation. The role involves close collaboration with software teams and requires understanding of complex networking concepts including packet processing, traffic conditioning, and telemetry.
As part of Google's hardware innovation team, you'll contribute to products that impact billions of users worldwide. The position offers the opportunity to work on groundbreaking data center networks, developing custom solutions that push the boundaries of performance and efficiency. You'll be involved in evaluating and implementing future ASIC designs, working with both custom and vendor solutions.
The ideal candidate brings strong experience in networking ASIC architecture, RTL development, and system design principles for low latency and high throughput systems. Knowledge of modern networking protocols, hardware-software interface optimization, and performance analysis is crucial. This role represents an opportunity to shape the future of Google's data center infrastructure while working with a diverse, world-class team of engineers.