Networking SoC Architect, Google Cloud
Description For Networking SoC Architect, Google Cloud
Google Cloud is seeking a Networking SoC Architect to join their Technical Infrastructure team. This role is crucial in developing custom silicon solutions that power Google's direct-to-consumer products. As part of the team defining solutions for network accelerations in data centers, you'll have multi-faceted responsibilities in project definition and close collaborations with software teams. The position involves designing and implementing next-generation data center accelerators, with a focus on performance analysis for end-to-end networking stacks using RDMA and packet processor-based transports. The Technical Infrastructure team is responsible for building and maintaining Google's data centers and platforms, ensuring optimal network performance and user experience. This role offers the opportunity to work with cutting-edge technology, collaborate with various stakeholders, and contribute to Google's innovative hardware solutions. The ideal candidate will bring extensive experience in network architecture, system design, and hardware/software interfaces, making a significant impact on Google's data center infrastructure.
Responsibilities For Networking SoC Architect, Google Cloud
- Evaluate different silicon solutions for executing Google's data center networking roadmap
- Create high performance hardware/software interfaces
- Collaborate closely with software, verification, emulation, physical design, packaging, and silicon validation stakeholders
- Drive vendor execution in various engagements, standard component roadmaps, build to specification, and co-developments
- Participate in evaluation of future ASIC designs and general architecture
Requirements For Networking SoC Architect, Google Cloud
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience
- 8 years of experience working in network architecture and system design principles
- Experience developing RTL for ASIC subsystems
- Experience in micro-architecture, design, verification, logic synthesis, and timing closure
- Experience in architecting RDMA or packet processor IPs across multiple generations
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