PCIe Silicon Validation Engineer

Google Cloud is seeking a PCIe Silicon Validation Engineer to join their diverse team that pushes boundaries in developing custom silicon solutions. This role involves taking ownership of the characterization of SERDES analog IPs provided by external vendors, ensuring they meet Google's high standards. The position requires working closely with different multi-functional teams within Google's Silicon organization and external vendors.

As a PCIe Silicon Validation Engineer, you will be responsible for validating SERDES IPs, such as PCIeG6 PHYs, writing in-house tools and scripts for IP characterization, and demonstrating the characterization, bench testing, and debugging of analog/mixed signal on-chip circuitry. You will also develop electrical tests and automate test processes using various tools and interfaces.

The ideal candidate should have a strong background in Electronic or Computer Engineering, with at least 10 years of experience working with PLLs, PCIe, and SerDes IPs. Experience in SerDes design and architecture, including CDR and equalization, is crucial. Familiarity with lab equipment such as BERT, real-time scopes, Spectrum Analyzers, VNA, and protocol analyzers is required.

This position offers the opportunity to contribute to the innovation behind products loved by millions worldwide, shaping the next generation of hardware experiences and delivering unparalleled performance, efficiency, and integration. Join Google's Technical Infrastructure team and be part of the engineering force that makes Google's product portfolio possible.

Google is committed to diversity, equality, and creating a culture of belonging. They offer equal employment opportunities regardless of background and provide accommodations for applicants with special needs. This role requires English proficiency to facilitate efficient global collaboration and communication.