RTL Design Engineer, Google Cloud

In this role, you will use your ASIC design experience to be part of a team that creates the SoC Very Large Scale Integration (VLSI) design cycle from start to finish. You will collaborate with design and verification engineers in projects, creating architecture definitions with RTL coding, and running block level simulations. You will contribute in all phases of complex Application-Specific Integrated Circuit (ASIC) designs from design specification to production. Additionally, you will collaborate with members of architecture, software, verification, power, timing, synthesis and etc to specify and deliver high quality SoC/RTL. You will solve technical problems with innovative micro-architecture and practical logic solutions, and evaluate design options with complexity, performance, power and area in mind.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

Responsibilities: • Define the block level design document such as interface protocol, block diagram, transaction flow, pipeline, etc. • Perform RTL development (e.g., coding and debug in Verilog, SystemVerilog, VHDL), function/performance simulation debug, and Lint/CDC/FV/UPF checks. • Participate in synthesis, timing/power closure, and FPGA/silicon bring-up. • Participate in test plan and coverage analysis of the block and SOC-level verification. • Communicate and work with multi-disciplined and multi-site teams.