RTL Design Engineer, Google Cloud

Google is a global technology leader that develops innovative products and services used by millions worldwide.
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Mid-Level Software Engineer
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5,000+ Employees
5+ years of experience
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Description For RTL Design Engineer, Google Cloud

Google Cloud is seeking an RTL Design Engineer to join their Technical Infrastructure team. This role focuses on developing custom silicon solutions that power Google's direct-to-consumer products. As an RTL Design Engineer, you'll work on Application-Specific Integrated Circuit (ASIC) design, creating System on a Chip (SoC) solutions from conception to production. You'll collaborate with various teams including architecture, software, verification, power, timing, and synthesis to deliver high-quality SoC/RTL designs. The role involves innovative micro-architecture development, practical logic solutions, and optimization for performance, power, and area. You'll be part of the team that maintains Google's data centers and builds next-generation platforms, ensuring users have the best and fastest experience possible. The position offers the opportunity to work on groundbreaking technology that impacts millions of users worldwide, while being part of a diverse team that pushes boundaries in hardware development.

Last updated 24 days ago

Responsibilities For RTL Design Engineer, Google Cloud

  • Lead a complex ASIC subsystem
  • Understand how it interacts with software and other ASIC subsystems to implement groundbreaking data centers
  • Define high-performance hardware/software interfaces. Write micro architecture and design specifications
  • Define efficient micro-architecture and block partitioning/interfaces and flows
  • Collaborate closely with software, verification, and physical design stakeholders to ensure the designs are complete, correct, and performant

Requirements For RTL Design Engineer, Google Cloud

Python
  • Bachelor's degree in Electrical Engineering or equivalent practical experience
  • 5 years of experience with RTL development for ASIC subsystems using Verilog
  • Experience with speed interfaces such as PCIe, InfiniBand, and their low latency, security, and reliability principles
  • Experience with micro architecture, design, verification, logic synthesis, and timing closure

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