RTL Design Engineer, Security
Description For RTL Design Engineer, Security
Google is seeking a skilled RTL Design Engineer to join their Security team in Bengaluru. This role is crucial in developing custom silicon solutions that power Google's direct-to-consumer products. The position focuses on Register-Transfer Level (RTL) design development of security IP and subsystems, including microarchitecture, RTL coding, and various optimizations.
As part of Google's mission to organize the world's information and make it universally accessible, you'll work with a team that combines the best of Google AI, Software, and Hardware to create innovative experiences. The role involves detailed technical work with RTL implementations, test planning, and system optimization.
The ideal candidate will have strong experience in RTL digital logic design using System Verilog, along with expertise in scripting languages and optimization techniques. This position offers the opportunity to contribute to products used by millions worldwide while working with cutting-edge technology in hardware security.
You'll be part of a diverse team that pushes boundaries in hardware development, working on projects that require both technical expertise and innovative thinking. The role combines security expertise with hardware design, making it an exciting opportunity for someone passionate about creating secure hardware solutions at scale.
This position at Google offers the chance to work on next-generation hardware experiences, delivering unparalleled performance, efficiency, and integration. You'll be at the forefront of hardware security development, working with a team that values diversity and innovation while contributing to products that have global impact.
Responsibilities For RTL Design Engineer, Security
- Participate in test planning and coverage analysis
- Develop RTL implementations that meet power, performance and area goals
- Participate in synthesis, timing/power closure and FPGA and silicon bring-up
- Perform Verilog/SystemVerilog RTL coding, functional, performance simulation debug and Lint/CDC/FV/UPF checks
- Create tools/scripts to automate tasks and track progress
Requirements For RTL Design Engineer, Security
- 5 years of experience in designing RTL digital logic using System Verilog for FPGA/ASIC
- Experience in scripting language such as Perl or Python
- Experience in area, power and performance optimization
- Master's degree or PhD in Electrical Engineering, Computer Science, or equivalent practical experience (preferred)
- Experience in design and development of security blocks or crypto blocks (preferred)
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