RTL Design Engineer, University Graduate, PhD, Machine Learning
Description For RTL Design Engineer, University Graduate, PhD, Machine Learning
Google's ML, Systems, & Cloud AI (MSCA) organization is seeking a RTL Design Engineer to join their team developing custom silicon solutions for Google's direct-to-consumer products. This role combines hardware engineering with machine learning applications, focusing on designing and implementing hardware infrastructure that powers Google's services and Cloud platform. The position requires a PhD in relevant fields and expertise in RTL coding and SystemVerilog. The successful candidate will work on clock control subsystems, develop RTL implementations, and collaborate with various teams including architecture, power, and design validation. The role offers competitive compensation ($132,000-$189,000 plus bonus and equity) and the opportunity to impact billions of users through Google's services. The position is available in Madison, WI or Sunnyvale, CA, and involves working with cutting-edge technology including TPUs and the Vertex AI platform. This is an excellent opportunity for someone interested in pushing the boundaries of hardware design while contributing to Google's next generation of products and services.
Responsibilities For RTL Design Engineer, University Graduate, PhD, Machine Learning
- Work mostly independently to create and review clock control subsystem's design microarchitecture specifications
- Develop SystemVerilog RTL to implement logic for ASIC products according to established coding and quality guidelines
- Work with architecture and power teams to evaluate features and their impact
- Work with design validation (DV) teams to create test plans to verify, and debug design RTL
- Work with physical design teams to ensure design meets physical requirements and timing closure
Requirements For RTL Design Engineer, University Graduate, PhD, Machine Learning
- PhD degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience
- Academic, educational, internship, or project experience with RTL coding and Verilog/SystemVerilog
- Experience with digital clock control circuits (preferred)
- Experience with a scripting language (e.g., Python or Perl) (preferred)
- Knowledge of processor design or accelerators (preferred)
- Knowledge of high-performance and low power design techniques (preferred)
Benefits For RTL Design Engineer, University Graduate, PhD, Machine Learning
- Bonus
- Equity
- Comprehensive benefits package
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