Senior ASIC Design Engineering, Silicon
Description For Senior ASIC Design Engineering, Silicon
Google is seeking a Senior ASIC Design Engineer to join their hardware team, focusing on developing custom silicon solutions for direct-to-consumer products. This role combines cutting-edge hardware development with Google's innovative approach to technology. The position requires expertise in RTL design, microarchitecture, and low-power optimization, making it perfect for engineers passionate about pushing the boundaries of hardware design.
The role involves working on products that impact millions of users worldwide, requiring strong technical skills in Verilog/System Verilog, RTL design, and quality sign-off flows. You'll be responsible for defining microarchitecture details, performing RTL development, and ensuring quality through various checks and optimizations.
As part of Google's diverse team, you'll contribute to the next generation of hardware experiences, focusing on performance, efficiency, and integration. The position offers the opportunity to work with cutting-edge technology while being part of a company that values innovation and technical excellence.
This is an excellent opportunity for experienced hardware engineers who want to impact consumer technology at a global scale. The role combines technical depth with the chance to work on products that directly influence how people interact with technology. You'll be part of a team that pushes boundaries in silicon design while contributing to Google's mission of organizing the world's information and making it universally accessible and useful.
Responsibilities For Senior ASIC Design Engineering, Silicon
- Define microarchitecture details such as interface protocol, block diagram, data flow, pipelines, etc.
- Perform Register-Transfer Level (RTL) development (SystemVerilog), RTL integration (Perl), debug functional/performance simulations
- Perform RTL quality checks including Lint, CDC, RDC, Synthesis, Unified Power Format (UPF) checks
Requirements For Senior ASIC Design Engineering, Silicon
- Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience
- 3 years of experience with Register-Transfer Level (RTL) design using Verilog/System Verilog and microarchitecture
- Experience in handling low power schemes, power roll up and power estimations
- Experience in Register-Transfer Level (RTL) quality sign-off flows (e.g., CDC, RDC, Lint, Power Intent or LEC)
- Experience with Perl or Python
Jobs Related To Google Senior ASIC Design Engineering, Silicon
