Senior ASIC Design Engineering, Silicon
Description For Senior ASIC Design Engineering, Silicon
Google is seeking a Senior ASIC Design Engineer to join their hardware team in Bengaluru. This role is crucial in developing custom silicon solutions that power Google's direct-to-consumer products. As part of a diverse team, you'll be at the forefront of innovation, working on hardware that impacts millions of users worldwide.
The position requires strong expertise in Register-Transfer Level (RTL) design, with a focus on microarchitecture and low power schemes. You'll be responsible for defining critical microarchitecture details, performing RTL development using SystemVerilog, and ensuring quality through various checks and validations.
The ideal candidate should have at least 3 years of experience in RTL design and microarchitecture, with a solid background in electrical engineering or computer science. Knowledge of low power schemes, power estimation, and RTL quality sign-off flows is essential. Experience with Perl or Python is required, and familiarity with computer architecture is a plus.
This role offers the opportunity to work with cutting-edge technology at one of the world's leading tech companies. You'll be contributing to the next generation of hardware experiences, focusing on performance, efficiency, and integration. The position combines technical challenges with the satisfaction of creating products that make a real difference in people's lives.
Google offers a collaborative environment where diversity is valued and innovation is encouraged. The company is committed to creating a culture of belonging and provides equal employment opportunities to all candidates. This role is perfect for someone who wants to be at the intersection of hardware innovation and consumer impact, working on projects that push the boundaries of what's possible in computing.
Responsibilities For Senior ASIC Design Engineering, Silicon
- Define microarchitecture details such as interface protocol, block diagram, data flow, pipelines, etc.
- Perform Register-Transfer Level (RTL) development (SystemVerilog), RTL integration (Perl), debug functional/performance simulations
- Perform RTL quality checks including Lint, CDC, RDC, Synthesis, Unified Power Format (UPF) checks
Requirements For Senior ASIC Design Engineering, Silicon
- Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience
- 3 years of experience with Register-Transfer Level (RTL) design using Verilog/System Verilog and microarchitecture
- Experience in handling low power schemes, power roll up and power estimations
- Experience in Register-Transfer Level (RTL) quality sign-off flows (e.g., CDC, RDC, Lint, Power Intent or LEC)
- Experience with Perl or Python
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science (preferred)
- Experience with methodologies for low power estimation, timing closure, and synthesis (preferred)
- Experience with computer architecture (preferred)
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