Senior ASIC Design Performance Verification Engineer
Description For Senior ASIC Design Performance Verification Engineer
Google is seeking a Senior ASIC Design Performance Verification Engineer to join their hardware team in Bengaluru. This role is crucial in developing custom silicon solutions that power Google's direct-to-consumer products. The position requires extensive experience in digital simulation and performance verification, with a focus on SystemVerilog and UVM.
The ideal candidate will be responsible for developing and executing performance verification test plans for next-generation configurable infrastructure IPs, interconnects, and memory subsystems. They will work with cutting-edge technologies and contribute to products used by millions worldwide.
This role offers the opportunity to work at the intersection of AI, software, and hardware, developing solutions that push the boundaries of computing performance and efficiency. The engineer will be part of Google's mission to create radically helpful experiences through technology innovation.
Key responsibilities include analyzing performance data, conducting reviews with architecture and design teams, and working with constrained-random verification environments. The role requires expertise in various technical areas such as Caches Hierarchies, Memory Consistency Models, and Interconnect Protocols.
As part of Google's hardware team, you'll contribute to the next generation of hardware experiences, working alongside talented engineers and architects. The position offers the chance to impact Google's future hardware products while being part of a company known for its innovative technology solutions and global reach.
Google provides a collaborative environment and is committed to diversity, equity, and inclusion. They offer comprehensive benefits and support for professional growth, making it an excellent opportunity for experienced engineers looking to make a significant impact in hardware development.
Responsibilities For Senior ASIC Design Performance Verification Engineer
- Develop a performance verification test plan from architecture specifications and goals; analyze performance data and conduct reviews with architecture and design teams to get a sign-off
- Plan and execute the performance verification of the next generation configurable infrastructure Internet Protocols (IPs), interconnects and memory subsystems
- Use constrained-random verification environments and develop stimulus, enhance existing performance monitors and scoreboard infrastructure using SystemVerilog and Universal Verification Methodology (UVM)
- Verify the impact of low power optimization on performance
Requirements For Senior ASIC Design Performance Verification Engineer
- Bachelor's degree in Electrical Engineering or Computer Science or equivalent practical experience
- 5 years of experience in simulating digital reasoning at Register-Transfer Level (RTL) level using SystemVerilog and UVM
- 5 years of experience in performance verification for IPs
- Experience in Caches Hierarchies, Coherency, Memory Consistency Models, DDR/LPDDR, PCIe, Packet Processors, Security, or Clock and Power Controllers (Preferred)
- Experience with Interconnect Protocols (e.g., AHB, AXI, ACE, CHI, CCIX, CXL) (Preferred)
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