Senior CPU Design Verification Engineer

Google is a global technology company that develops and provides a wide range of internet-related services and products.
Embedded
Senior Software Engineer
In-Person
5,000+ Employees
8+ years of experience
AI · Enterprise SaaS

Description For Senior CPU Design Verification Engineer

Google is seeking a Senior CPU Design Verification Engineer to join their Technical Infrastructure team. This role is crucial in developing custom silicon solutions that power Google's direct-to-consumer products. As part of a diverse team, you'll contribute to the innovation behind products used by millions worldwide, shaping the next generation of hardware experiences.

The position involves working on the architecture that supports Google's entire product portfolio. You'll be responsible for planning and executing verification of digital design blocks, creating and enhancing verification environments, and ensuring the functional correctness of designs. This role requires expertise in digital logic design principles, RTL concepts, and languages like Verilog or SystemVerilog.

Key responsibilities include interacting with design engineers, creating constrained-random verification environments, identifying and writing coverage measures, debugging tests, and closing coverage measures to track progress towards tape-out. The ideal candidate will have a strong background in Electrical Engineering or Computer Science, with experience in UVM, SystemVerilog, and scripting languages.

Google offers a collaborative environment where you'll work with cutting-edge technology and contribute to products that impact users globally. The company is committed to diversity, equality, and creating a culture of belonging. This position provides an opportunity to work on challenging projects at the forefront of hardware innovation, making it an exciting prospect for experienced verification engineers looking to make a significant impact in the tech industry.

Last updated 10 days ago

Responsibilities For Senior CPU Design Verification Engineer

  • Plan the verification of digital design blocks by understanding the design specification and interacting with design engineers to identify important verification scenarios
  • Create and enhance constrained-random verification environments using SystemVerilog/UVM or Specman
  • Identify and write all types of coverage measures for stimulus and corner-cases
  • Debug tests with design engineers to deliver functionally correct design blocks
  • Close coverage measures to identify verification holes and to show progress towards tape-out

Requirements For Senior CPU Design Verification Engineer

Python
  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience
  • 8 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog
  • Experience with UVM, SystemVerilog, or other scripting languages (e.g., Python, Perl, Shell, Bash, etc.)
  • Familiarity with CPU implementation, assembly language, or compute SOCs

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