Senior Design For Testability Engineer, Silicon
Description For Senior Design For Testability Engineer, Silicon
Google is seeking a Senior Design For Testability Engineer to join their silicon team, focusing on developing custom silicon solutions for Google's direct-to-consumer products. This role combines hardware expertise with Google's cutting-edge technology to create innovative solutions that power millions of users worldwide.
The position requires deep expertise in Design for Testability (DFT) and Design for Debug (DFD) methodologies, with a strong focus on implementing and verifying various testing mechanisms for complex silicon designs. You'll work with memory built-in self test (MBIST), scan chains, DFT compression, and various other testing methodologies.
As a senior engineer, you'll collaborate with silicon engineering teams to develop test plans, generate patterns, and participate in post-silicon activities. The role demands expertise in industry-standard EDA tools and test standards, making it perfect for someone who enjoys working at the intersection of hardware design and testing methodologies.
The ideal candidate will have a strong background in electrical engineering or computer science, with significant experience in DFT/DFD flows. You'll be part of Google's mission to create radically helpful experiences through technology, working on next-generation hardware that pushes the boundaries of performance and efficiency.
This role offers the opportunity to work with cutting-edge technology, collaborate with world-class engineers, and contribute to products that impact millions of users. You'll be at the forefront of silicon innovation, helping Google maintain its leadership in hardware development while ensuring the highest quality and reliability standards.
Responsibilities For Senior Design For Testability Engineer, Silicon
- Define Design for Excellence (DFX) specifications and develop flows and methodologies for new technology node implementation
- Implement/Integrate and verify Design for Testing (DFT) logic
- Work with silicon engineering team to create test plans and generate test patterns
- Participate in post-silicon activity like bring up, diagnostics and characterization
- Work with EDA and IP vendors to incorporate state-of-the-art DFT/DFD/DFY flows and methodologies
Requirements For Senior Design For Testability Engineer, Silicon
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience
- 5 years of experience in DFT/DFD flows and methodologies
- Experience working with fault modeling, test standards and industry DFT/DFD/ATPG tools
- Experience with Application-Specific Integrated Circuits (ASIC) DFT, synthesis, simulation and verification flow
- Experience developing DFT specifications and driving DFT architecture
- Experience using EDA tools like Design Compiler, DFT Max, FastScan, TetraMax, Tessent, SpyGlass, Modus, and TestKompress
- Experience with User Defined Fault Models (UDFM) and other fault models
- Knowledge of various Test standards (IEEE 1149.10, 1149.6, 1500, 1687) and test formats
Benefits For Senior Design For Testability Engineer, Silicon
- Equal opportunity employer
- Accommodation for special needs
- Comprehensive benefits package
Jobs Related To Google Senior Design For Testability Engineer, Silicon
