Senior Multimedia Design Verification Engineer
Description For Senior Multimedia Design Verification Engineer
Google is seeking a Senior Multimedia Design Verification Engineer to join their hardware team. This role is crucial in developing custom silicon solutions that power Google's direct-to-consumer products. You'll be part of a diverse team that pushes boundaries and contributes to innovations behind products used by millions worldwide. The position involves leading verification efforts for multimedia IPs, working with cutting-edge technology, and ensuring the quality of hardware solutions.
As a Senior Multimedia Design Verification Engineer, you'll collaborate with architecture and design engineers to identify crucial verification scenarios, create sophisticated verification environments, and ensure the functionality of design blocks. Your expertise in UVM, System Verilog, and multimedia IP verification will be essential in delivering high-quality silicon solutions.
The role offers the opportunity to work on next-generation hardware experiences, focusing on unparalleled performance, efficiency, and integration. You'll be at the intersection of Google's AI, Software, and Hardware initiatives, helping to create radically helpful experiences for users worldwide. This position requires strong technical leadership, deep verification expertise, and the ability to drive complex projects to completion.
Working at Google means being part of a company that values diversity, equality, and inclusion. You'll have the chance to impact millions of users while working with some of the industry's best minds in silicon development. The role offers the perfect blend of technical challenges and leadership opportunities, making it ideal for experienced verification engineers looking to make a significant impact in consumer technology.
Responsibilities For Senior Multimedia Design Verification Engineer
- Plan the verification of multimedia Intellectual Properties (IPs) at Subsystem and full chip level
- Create and enhance constrained-random verification environments using System Verilog and Universal Verification Methodology (UVM)
- Identify and write all types of coverage measures for stimulus and corner-cases
- Debug tests with design engineers to deliver functionally correct design blocks
- Close coverage measures to identify verification holes and to show progress towards tape-out
Requirements For Senior Multimedia Design Verification Engineer
- Bachelor's degree in Electrical Engineering or Computer Science, or related field, or equivalent practical experience
- 10 years of industry experience in Design Verification
- Experience leading a team completing the full functional verification and performance validation cycle of subsystems
- Experience constructing reusable verification components and environments using UVM
Benefits For Senior Multimedia Design Verification Engineer
- Equal opportunity employer
- Accommodation for disabilities
- Inclusive work environment
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