Senior Network Design Verification Engineer
Description For Senior Network Design Verification Engineer
Google Cloud is seeking a Senior Network Design Verification Engineer to join their Technical Infrastructure team. This role is crucial in developing custom silicon solutions that power Google's direct-to-consumer products. As part of the R&D team, you'll be responsible for building verification components, conducting constrained-random testing, and managing system testing and verification closure. You'll work directly with design and verification engineers to ensure the highest quality of digital designs.
The position requires expertise in digital reasoning verification at RTL level, with a strong foundation in networking protocols and system design principles. You'll be working on cutting-edge technology that ensures Google's networks maintain optimal performance and reliability. The role combines technical depth in verification methodologies with practical application in high-stakes environments.
This is an excellent opportunity for experienced verification engineers who want to impact products used by millions globally. You'll be part of Google's Technical Infrastructure team, which is fundamental to keeping Google's vast product portfolio running smoothly. The team takes pride in being "engineers' engineers" and maintains Google's data centers and platforms.
The ideal candidate will have strong experience with SystemVerilog or Specman/E, understanding of networking protocols, and proven ability in verification planning and execution. You'll be working in either Tel Aviv or Haifa, contributing to Google's next generation of hardware experiences while focusing on unparalleled performance, efficiency, and integration.
Responsibilities For Senior Network Design Verification Engineer
- Plan the verification of digital design blocks by understanding design specification
- Create and enhance constrained-random verification environments using SystemVerilog
- Identify and write all types of coverage measures for stimulus and corner-cases
- Debug tests with design engineers to deliver functionally correct design blocks
- Close coverage measures to identify verification holes and show progress towards tape-out
Requirements For Senior Network Design Verification Engineer
- Bachelor's degree in Electrical Engineering or equivalent practical experience
- 5 years of experience verifying digital reasoning at Register-Transfer Level (RTL) using SystemVerilog or Specman/E for FPGAs or ASIC
- Experience working with design networking like RDMA or packet processing
- Experience in creating and using verification components and environments in standard verification methodology
Benefits For Senior Network Design Verification Engineer
- Equal opportunity employer
- Accommodation for special needs
- Global work environment
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