Senior Network Design Verification Engineer
Description For Senior Network Design Verification Engineer
Google Cloud is seeking a Senior Network Design Verification Engineer to join their Technical Infrastructure team. This role is crucial in developing custom silicon solutions that power Google's direct-to-consumer products. As part of the R&D team, you'll be responsible for building verification components, implementing constrained-random testing, and managing system testing and verification closure.
The position involves working with cutting-edge technology in Google's Technical Infrastructure team, where you'll help maintain and develop data centers and next-generation Google platforms. You'll be verifying digital designs and collaborating with design and verification engineers on various projects. Your work will directly impact the architecture that keeps Google's services running smoothly and efficiently.
The ideal candidate should have strong experience in digital verification, particularly with SystemVerilog or Specman/E, and a deep understanding of networking protocols and system design principles. You'll be working on projects that require expertise in performance verification, ASIC components, and memory system architecture.
This role offers the opportunity to work on technology that impacts millions of users worldwide, alongside talented engineers who are passionate about innovation and technical excellence. You'll be part of a team that takes pride in solving complex technical challenges and maintaining Google's high-performance infrastructure.
The position requires a combination of technical expertise, collaborative skills, and the ability to manage complex verification processes from planning to completion. You'll be contributing to Google's mission of building robust and efficient hardware solutions while working with state-of-the-art technology and methodologies.
Responsibilities For Senior Network Design Verification Engineer
- Plan the verification of digital design blocks by understanding design specification
- Create and enhance constrained-random verification environments using SystemVerilog
- Identify and write all types of coverage measures for stimulus and corner-cases
- Debug tests with design engineers to deliver functionally correct design blocks
- Close coverage measures to identify verification holes and show progress towards tape-out
Requirements For Senior Network Design Verification Engineer
- Bachelor's degree in Electrical Engineering or equivalent practical experience
- 5 years of experience verifying digital reasoning at Register-Transfer Level (RTL) using SystemVerilog or Specman/E for FPGAs or ASIC
- Experience working with design networking like RDMA or packet processing
- Experience in creating and using verification components and environments in standard verification methodology
- Experience in TCP, IP, Ethernet, PCIE and DRAM, NoC principles and protocols
- Experience with verification techniques and full verification life cycle
Benefits For Senior Network Design Verification Engineer
- Equal opportunity employer
- Accommodation for special needs
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