Senior Physical Design Engineer, Mixed Signal, Silicon
Description For Senior Physical Design Engineer, Mixed Signal, Silicon
Google is seeking a Senior Physical Design Engineer to join their hardware team focused on developing custom silicon solutions for direct-to-consumer products. This role combines hardware expertise with Google's cutting-edge AI and software capabilities to create next-generation computing experiences. The position requires deep knowledge of physical design, including Place and Route (PnR), Static Timing Analysis (STA), and power integrity analysis.
As a Senior Physical Design Engineer, you'll work on projects that directly impact millions of users worldwide through Google's consumer products. You'll collaborate with front-end designers and back-end physical design integration engineers to deliver high-quality silicon solutions. The role demands expertise in modern design tools and methodologies, including DRC, LVS signoff, and EMIR analysis.
The ideal candidate will have at least 5 years of experience in physical design, with a strong background in ASIC development and scripting languages. You'll be part of a diverse team that pushes boundaries in hardware innovation, working on projects that require both technical excellence and creative problem-solving.
This position offers the opportunity to work at the intersection of hardware and software, contributing to Google's mission of organizing the world's information and making it universally accessible. You'll be involved in developing custom silicon solutions that power future Google products, focusing on performance, efficiency, and integration.
The role combines technical challenges with the excitement of working on consumer-facing products, making it ideal for engineers who want to see their work make a direct impact on users' lives. You'll be part of Google's commitment to innovation in hardware development, working with cutting-edge technologies and methodologies.
Responsibilities For Senior Physical Design Engineer, Mixed Signal, Silicon
- Generate high-quality Place and Route (PnR) results for digital blocks, including DRC and LVS signoff
- Monitor timing of blocks with modern Static Timing Analysis (STA) tools and techniques
- Analyze designs based on key metrics, including power, area, and performance trade-off
- Apply engineering best practices to the design and implementation of ASIC blocks
- Analyze power integrity Electromagnetic migration and IR drop (EMIR) of blocks and implement fixes
Requirements For Senior Physical Design Engineer, Mixed Signal, Silicon
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience
- 5 years of experience in physical design
- Experience with PnR/APR, STA, EMIR, and DRC tools/flows working on synthesized designs
- Experience in one or more scripting languages (e.g., Tcl, Python, etc.)
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