Senior Register-Transfer Level Design Engineer, Core IP, Silicon
Description For Senior Register-Transfer Level Design Engineer, Core IP, Silicon
Google is seeking a Senior Register-Transfer Level Design Engineer to join their Devices & Services team, focusing on developing custom silicon solutions for Google's direct-to-consumer products. This role combines hardware expertise with cutting-edge technology to create innovative solutions that power Google's next-generation hardware experiences.
The position requires deep expertise in RTL design, ASIC methodologies, and system architecture. You'll be working on microarchitecture definition for Core IP hardware designs, developing RTL implementations, and ensuring optimal power, performance, and area goals are met. The role involves collaboration with multi-disciplinary teams across different locations, contributing to various stages of the design process from verification to silicon bring-up.
As part of Google's hardware innovation team, you'll have the opportunity to impact millions of users worldwide through the development of custom silicon solutions. The role offers exposure to advanced technologies including Machine Learning Accelerators, Camera ISP image processing, and multimedia IPs.
The ideal candidate will have extensive experience in RTL design, strong programming skills, and a deep understanding of hardware architecture. This position offers the chance to work with cutting-edge technology while contributing to Google's mission of making information universally accessible and useful through hardware innovation.
Working at Google means joining a company committed to diversity, equity, and inclusion, offering comprehensive benefits and the opportunity to shape the future of hardware technology. You'll be part of a team that pushes boundaries and creates radically helpful experiences for users worldwide.
Responsibilities For Senior Register-Transfer Level Design Engineer, Core IP, Silicon
- Provide microarchitecture definition for Core IP hardware designs and subsystem/ASIC top-level integration
- Define and develop Register-Transfer Level (RTL) implementations that meet engaged power, performance and area goals
- Perform RTL coding, function/performance simulation debug and Lint/CDC/FV/UPF checks. Participate in synthesis, timing/power closure, and FPGA/silicon bring-up
- Participate in test plan and coverage analysis of the sub-system and chip-level verification
- Create tools/scripts to automate tasks and track progress. Work with multi-disciplined and multi-site teams in RTL design, verification, or architecture/micro-architecture planning
Requirements For Senior Register-Transfer Level Design Engineer, Core IP, Silicon
- Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience
- 10 years of work experience in RTL design
- Experience with ASIC design methodologies for clock domain checks and reset checks
- Experience in RTL coding using System Verilog/Verilog
Benefits For Senior Register-Transfer Level Design Engineer, Core IP, Silicon
- Equal opportunity employer
- Accommodation for special needs
- Global work environment
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