Senior Register-Transfer Level Design Engineer, Core IP, Silicon

Google's Devices & Services team is seeking a Senior Register-Transfer Level Design Engineer to join their innovative hardware development team. This role combines cutting-edge silicon design with Google's mission to create radically helpful experiences for users worldwide. As a senior RTL engineer, you'll work on custom silicon solutions that power Google's direct-to-consumer products, focusing on Core IP hardware designs and ASIC integration.

The position requires deep expertise in RTL design, with responsibilities spanning from microarchitecture definition to implementation and verification. You'll be working with state-of-the-art ASIC design methodologies, developing solutions that meet stringent power, performance, and area goals. The role involves collaboration with multi-disciplined teams across different sites, contributing to various aspects of the design process from RTL coding to FPGA/silicon bring-up.

This is an excellent opportunity for experienced hardware engineers who want to impact millions of users through Google's hardware products. You'll be part of a diverse team that pushes boundaries in custom silicon development, working on next-generation hardware experiences that deliver unparalleled performance and efficiency. The role offers exposure to cutting-edge technologies, including Machine Learning Accelerators, Camera ISP processing, and multimedia IPs.

The ideal candidate will bring strong technical skills in System Verilog/Verilog, ASIC design methodologies, and hardware optimization. You'll have the chance to work on complex technical challenges while contributing to Google's mission of making technology more accessible and useful for everyone. The position offers the opportunity to work with industry-leading experts in a collaborative environment that values innovation and technical excellence.