Senior RTL Design Engineer
Description For Senior RTL Design Engineer
Google Cloud is seeking a Senior RTL Design Engineer to join their Technical Infrastructure team. This role focuses on developing custom silicon solutions that power Google's direct-to-consumer products. You'll be working on Application-Specific Integrated Circuit (ASIC) design as part of a team creating System on Chip (SoC) designs from conception to production.
The position involves collaborating with various teams including architecture, software, verification, power, timing, and synthesis to deliver high-quality SoC/RTL solutions. You'll be responsible for leading complex ASIC subsystems, defining hardware/software interfaces, and creating innovative micro-architectural solutions while considering performance, power, and area optimization.
As part of Google's Technical Infrastructure team, you'll contribute to the backbone that keeps Google's vast product portfolio running smoothly. The team is responsible for developing and maintaining data centers and building next-generation Google platforms. The role offers the opportunity to work with cutting-edge technology and contribute to groundbreaking data center implementations.
The ideal candidate should have strong experience in RTL development, particularly with Verilog, and be familiar with various speed interfaces such as PCIe and InfiniBand. Knowledge of FPGA, emulation platforms, and SoC architecture is highly valued. This position offers the chance to work with a diverse team that pushes boundaries and develops solutions used by millions of users worldwide.
Working at Google provides the opportunity to be part of a company committed to diversity, equality, and inclusion. The role offers the chance to work on innovative projects while collaborating with some of the best minds in the industry. Join us in shaping the future of hardware experiences and delivering unparalleled performance, efficiency, and integration in Google's infrastructure.
Responsibilities For Senior RTL Design Engineer
- Lead a complex ASIC subsystem
- Understand how it interacts with software and other ASIC subsystems to implement groundbreaking data center
- Define high-performance hardware/software interfaces
- Write micro architecture and design specifications
- Define efficient micro-architecture and block partitioning/interfaces and flows
- Collaborate closely with software, verification, and physical design stakeholders
Requirements For Senior RTL Design Engineer
- Bachelor's degree in Electrical Engineering or equivalent practical experience
- 5 years of experience with RTL development for ASIC subsystems using Verilog
- Experience with speed interfaces such as PCIe, InfiniBand
- Experience with micro architecture, design, verification, logic synthesis, and timing closure
- Knowledge of arithmetic units, bus architectures, processor design, accelerators, or memory hierarchies
- Knowledge of high performance and low power design techniques
- Knowledge of FPGA, emulation platforms, and SoC architecture
- Knowledge of assertion-based formal verification
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