Senior RTL Design Engineer
Description For Senior RTL Design Engineer
Join Google's Technical Infrastructure team as a Senior RTL Design Engineer, where you'll be at the forefront of developing custom silicon solutions that power Google's direct-to-consumer products. This role focuses on ASIC design and System on Chip (SoC) development, requiring expertise in RTL development and hardware architecture.
You'll be part of a diverse team that pushes boundaries in hardware innovation, working on projects from initial design specification to production. The position involves collaborating with various teams including architecture, software, verification, power, timing, and synthesis to deliver high-quality SoC/RTL solutions.
As a Senior RTL Design Engineer, you'll contribute to groundbreaking data center technologies, leading complex ASIC subsystems and defining high-performance hardware/software interfaces. The role requires strong technical skills in micro-architecture, design verification, and timing closure, with experience in interfaces like PCIe and InfiniBand.
The Technical Infrastructure team is proud to be the engineers' engineers, maintaining and developing Google's data centers and platforms. This role offers the opportunity to work on cutting-edge technology that directly impacts Google's vast product portfolio, ensuring users have the best and fastest experience possible.
This position is perfect for someone who combines deep technical expertise in RTL development with leadership capabilities and a passion for innovative hardware solutions. You'll be working in either Tel Aviv or Haifa, Israel, contributing to technology that powers services used by millions of people worldwide.
Responsibilities For Senior RTL Design Engineer
- Lead a complex ASIC subsystem
- Understand how it interacts with software and other ASIC subsystems to implement groundbreaking data center
- Define high-performance hardware/software interfaces. Write micro architecture and design specifications
- Define efficient micro-architecture and block partitioning/interfaces and flows
- Collaborate closely with software, verification, and physical design stakeholders to ensure the designs are complete, correct, and performant
Requirements For Senior RTL Design Engineer
- Bachelor's degree in Electrical Engineering or equivalent practical experience
- 5 years of experience with RTL development for ASIC subsystems using Verilog
- Experience with speed interfaces such as PCIe, InfiniBand, and their low latency, security, and reliability principles
- Experience with micro architecture, design, verification, logic synthesis, and timing closure
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