Senior RTL Design Engineer, Google Cloud
Description For Senior RTL Design Engineer, Google Cloud
Google Cloud is seeking a Senior RTL Design Engineer to join their Technical Infrastructure team. This role focuses on developing custom silicon solutions that power Google's direct-to-consumer products. You'll be working on Application-Specific Integrated Circuit (ASIC) design, creating System on a Chip (SoC) solutions from conception to production. The position involves collaborating with various teams including architecture, software, verification, power, timing, and synthesis to deliver high-quality SoC/RTL designs.
The role requires expertise in RTL development, micro-architecture design, and experience with high-speed interfaces. You'll be responsible for leading complex ASIC subsystems and defining hardware/software interfaces. The position offers the opportunity to work on groundbreaking data center technologies and contribute to the innovation behind products used by millions worldwide.
As part of Google's Technical Infrastructure team, you'll help build and maintain the architecture that keeps Google's product portfolio running smoothly. The team takes pride in being the engineers' engineers, focusing on developing and maintaining data centers and building next-generation Google platforms. This role is perfect for someone who enjoys solving complex technical problems with innovative micro-architecture and practical logic solutions, while considering performance, power, and area optimization.
The position offers the chance to work with cutting-edge technology in a collaborative environment, contributing to the future of Google's hardware experiences. You'll be part of a diverse team that pushes boundaries and delivers unparalleled performance, efficiency, and integration in custom silicon solutions.
Responsibilities For Senior RTL Design Engineer, Google Cloud
- Lead a complex ASIC subsystem
- Understand how it interacts with software and other ASIC subsystems to implement groundbreaking data center
- Define high-performance hardware/software interfaces. Write micro architecture and design specifications
- Define efficient micro-architecture and block partitioning/interfaces and flows
- Collaborate closely with software, verification, and physical design stakeholders to ensure the designs are complete, correct, and performant
Requirements For Senior RTL Design Engineer, Google Cloud
- Bachelor's degree in Electrical Engineering or equivalent practical experience
- 5 years of experience with RTL development for ASIC subsystems using Verilog
- Experience with speed interfaces such as PCIe, InfiniBand, and their low latency, security, and reliability principles
- Experience with micro architecture, design, verification, logic synthesis, and timing closure
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