Senior Silicon Design Verification Engineer, Security
Description For Senior Silicon Design Verification Engineer, Security
Google is seeking a Senior Silicon Design Verification Engineer to join their hardware team focused on developing custom silicon solutions for Google's direct-to-consumer products. This role combines Google's expertise in AI, Software, and Hardware to create innovative experiences. The position involves working on security-focused verification of silicon designs, requiring expertise in verification methodologies and languages like UVM and System Verilog. You'll collaborate with designers, architects, and stakeholders to develop test plans and ensure robust security implementation. The role demands strong technical skills in hardware verification, particularly in security IP and subsystems, as well as experience with ARM or RISC-V CPU based subsystems. As part of Google's mission to organize world's information and make it universally accessible, you'll contribute to developing next-generation hardware experiences that deliver unparalleled performance, efficiency, and integration. The position offers the opportunity to work with diverse teams and impact products used by millions worldwide.
Responsibilities For Senior Silicon Design Verification Engineer, Security
- Work with designer, architects and other stakeholders to come up with detailed test plans, dependencies and deliverables
- Plan the verification of security design blocks by fully understanding the design specification, security requirements and interacting with architecture and design engineers to identify important verification scenarios
- Create and enhance constrained-random verification environments using System Verilog and UVM
- Be the primary point of contact for functional verification of the IP for cross-functional teams
Requirements For Senior Silicon Design Verification Engineer, Security
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience
- 5 years of experience with verification methodologies and languages such as UVM and System Verilog
- Experience developing and maintaining verification testbenches, test cases, and test environments
- Experience with low power, debug, performance verification and use cases verification
- Experience with Security IP and subsystems
- Experienced in ARM or RISC-V CPU based subsystem verification
