Senior Silicon Design Verification Engineer, Security
Description For Senior Silicon Design Verification Engineer, Security
Google is seeking a Senior Silicon Design Verification Engineer to join their hardware team focused on developing custom silicon solutions for direct-to-consumer products. This role combines hardware expertise with Google's cutting-edge AI and software capabilities to create next-generation hardware experiences. The position requires strong verification experience with UVM and System Verilog, focusing on security design blocks and IP verification.
As a Senior Silicon Design Verification Engineer, you'll be instrumental in ensuring the quality and reliability of Google's custom silicon solutions. You'll work closely with designers, architects, and cross-functional teams to develop comprehensive test plans and verification environments. The role demands expertise in security IP and subsystems, with a focus on ARM or RISC-V CPU based subsystem verification.
The position offers the opportunity to work on products that impact millions of users worldwide, contributing to Google's mission of organizing world's information and making it universally accessible. You'll be part of a diverse team that pushes boundaries in hardware innovation, focusing on performance, efficiency, and integration.
Key responsibilities include creating detailed test plans, understanding security requirements, developing verification environments using System Verilog and UVM, and serving as the primary point of contact for IP functional verification. The ideal candidate will have at least 5 years of experience in verification methodologies and a strong background in electrical engineering or computer science.
This role is perfect for someone who wants to be at the forefront of hardware innovation, working with cutting-edge technology while contributing to products that have a global impact. You'll be part of Google's commitment to creating radically helpful experiences through the combination of AI, software, and hardware expertise.
Responsibilities For Senior Silicon Design Verification Engineer, Security
- Work with designer, architects and other stakeholders to come up with detailed test plans, dependencies and deliverables
- Plan the verification of security design blocks by fully understanding the design specification, security requirements and interacting with architecture and design engineers to identify important verification scenarios
- Create and enhance constrained-random verification environments using System Verilog and UVM
- Be the primary point of contact for functional verification of the IP for cross-functional teams
Requirements For Senior Silicon Design Verification Engineer, Security
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience
- 5 years of experience with verification methodologies and languages such as UVM and System Verilog
- Experience developing and maintaining verification testbenches, test cases, and test environments
- Experience with low power, debug, performance verification and use cases verification (preferred)
- Experience with Security IP and subsystems (preferred)
- Experienced in ARM or RISC-V CPU based subsystem verification (preferred)
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