Senior Silicon Digital RTL Design Engineer
Description For Senior Silicon Digital RTL Design Engineer
Google is seeking a Senior Silicon Digital RTL Design Engineer to join their hardware team focused on developing custom silicon solutions for direct-to-consumer products. This role combines cutting-edge hardware development with Google's mission to create radically helpful experiences.
As a Senior Silicon Digital RTL Design Engineer, you'll be working on innovative hardware solutions that power Google's consumer products used by millions worldwide. You'll be responsible for architecting, designing, and verifying digital logic using Verilog and SystemVerilog, while ensuring efficient implementation and integration with various system-on-chip subsystems.
The position requires strong expertise in digital logic design principles, RTL design concepts, and extensive experience with IP Development. You'll work closely with physical design teams to ensure efficient, low-power, and timing-clean physical implementation of digital logic designs. The role involves collaboration with cross-functional teams, including system architects and sub-system owners, to define specifications and chip functions.
This is an excellent opportunity for someone passionate about hardware design who wants to make a significant impact on Google's next generation of consumer products. You'll be part of a diverse team that pushes boundaries and innovates in custom silicon solutions, working with state-of-the-art technology and contributing to products that enhance people's daily lives.
The ideal candidate will have experience with low power design techniques, analog/mixed signal designs, and knowledge of highly scaled CMOS processes. Additional expertise in design-for-test flows, scripting languages, and version control systems will be valuable for this role.
Responsibilities For Senior Silicon Digital RTL Design Engineer
- Architect, design and verify digital logic using Verilog and SystemVerilog
- Interface with physical designers to generate high quality physical implementations through synthesis, place-and-route, timing closure and verification
- Engage with system architects and sub-system owners to define specifications and chip functions
- Perform power, area and performance trade-off analyses of digital designs and architectures
- Apply engineering best practices (e.g. code review, testing, refactoring) to the design and implementation of ASIC blocks
Requirements For Senior Silicon Digital RTL Design Engineer
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience
- 5 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog
- 5 years of experience with Intellectual Property (IP) Development or Integration
- Experience with low power design techniques
- Experience with Analog or Mixed Signal designs
- Experience working with highly scaled CMOS processes
- Experience with design-for-test (DFT) flows and methodology
- Experience in Python, TCL scripting languages
- Knowledge of version control systems such as Git
Benefits For Senior Silicon Digital RTL Design Engineer
- Equal opportunity employer
- Accommodation for disabilities
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