Senior SoC and IP Design Engineer
Description For Senior SoC and IP Design Engineer
Google Cloud is seeking a Senior SoC and IP Design Engineer to join their Technical Infrastructure team. This role offers an exciting opportunity to be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products.
As a Senior SoC and IP Design Engineer, you'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. You'll be working on cutting-edge technology, developing and maintaining data centers, and building the next generation of Google platforms.
Key responsibilities include defining SoC/block level design documents, performing RTL development, participating in synthesis and timing/power closure, and collaborating with multi-disciplined teams. You'll be working with advanced technologies such as Verilog, SystemVerilog, and various design verification tools.
The ideal candidate should have a strong background in electrical engineering or computer science, with extensive experience in digital logic design, RTL concepts, and low-power design techniques. Knowledge of high-performance design, assertion-based formal verification, and SoC architecture is highly valued.
Join Google Cloud and be at the forefront of hardware innovation, working on projects that directly impact millions of users worldwide. This role offers the chance to work with state-of-the-art technology and collaborate with some of the brightest minds in the industry. If you're passionate about pushing the boundaries of hardware design and want to make a significant impact on Google's product portfolio, this is the perfect opportunity for you.
Responsibilities For Senior SoC and IP Design Engineer
- Define the SoC/block level design document such as interface protocol, block diagram, transaction flow, pipeline etc.
- Perform Register-Transfer Level (RTL) development (e.g., coding and debug in Verilog, SystemVerilog), function/performance simulation debug and Lint/CDC/FV/UPF checks
- Participate in synthesis, timing/power closure and ASIC silicon bring-up
- Participate in test plan and coverage analysis of the block and SoC level verification
- Communicate and work with multi-disciplined and multi-site teams
Requirements For Senior SoC and IP Design Engineer
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience
- 5 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog
- Experience with logic synthesis techniques to optimize RTL code, performance and power as well as low-power design techniques
- Experience in logic design and debug with Design Verification (DV)
- Experience with design sign-off and quality tools (e.g., Lint, CDC, etc.)
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