Senior SoC and IP Design Engineer
Description For Senior SoC and IP Design Engineer
Google Cloud is seeking a Senior SoC and IP Design Engineer to join their Technical Infrastructure team. This role is crucial in developing custom silicon solutions that power Google's direct-to-consumer products. As part of the team, you'll be working on cutting-edge hardware architecture that keeps Google's vast infrastructure running smoothly.
The position offers an opportunity to work with state-of-the-art technology in SoC design, focusing on high-performance and low-power solutions. You'll be involved in the entire design process, from documentation to implementation and verification. The role requires expertise in RTL development, digital logic design, and various verification methodologies.
This is an excellent opportunity for experienced engineers who want to make a significant impact on Google's hardware infrastructure. You'll be working with multi-disciplined teams across different locations, contributing to products used by millions of users worldwide. The position requires strong technical skills in digital design, verification, and optimization, along with the ability to collaborate effectively with diverse teams.
The role is perfect for someone who enjoys pushing technical boundaries and solving complex problems in silicon design. You'll be working with cutting-edge tools and technologies, implementing advanced protocols like PCIe, UCIe, and DDR. The position offers the chance to work on projects that directly influence the performance and efficiency of Google's infrastructure.
As part of Google's Technical Infrastructure team, you'll be at the forefront of innovation, working with talented engineers who are passionate about building and optimizing hardware solutions. The role combines technical expertise with collaborative teamwork, making it an ideal position for engineers who want to grow their careers in a dynamic, challenging environment.
Responsibilities For Senior SoC and IP Design Engineer
- Define the SoC/block level design document such as interface protocol, block diagram, transaction flow, pipeline etc.
- Perform Register-Transfer Level (RTL) development (e.g., coding and debug in Verilog, SystemVerilog), function/performance simulation debug and Lint/CDC/FV/UPF checks
- Participate in synthesis, timing/power closure and ASIC silicon bring-up
- Participate in test plan and coverage analysis of the block and SoC level verification
- Communicate and work with multi-disciplined and multi-site teams
Requirements For Senior SoC and IP Design Engineer
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field, or equivalent practical experience
- 5 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog
- Experience with logic synthesis techniques to optimize RTL code, performance and power as well as low-power design techniques
- Experience in logic design and debug with Design Verification (DV)
- Experience with design sign-off and quality tools (e.g., Lint, CDC, etc.)
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