Senior SoC and IP Design Engineer
Description For Senior SoC and IP Design Engineer
Google Cloud is seeking a Senior SoC and IP Design Engineer to join their Technical Infrastructure team. This role is crucial in developing custom silicon solutions that power Google's direct-to-consumer products. As part of the team, you'll be working on cutting-edge hardware architecture that keeps Google's vast infrastructure running smoothly.
The position offers an opportunity to work with state-of-the-art technology in SoC design, focusing on high-performance and low-power solutions. You'll be involved in the entire design process, from documentation to implementation and verification. The role requires expertise in RTL development, digital logic design, and various verification methodologies.
Working at Google means joining a diverse team that pushes boundaries and innovates continuously. You'll be contributing to products used by millions of people worldwide, while collaborating with multi-disciplined teams across different locations. The Technical Infrastructure team takes pride in being the engineers' engineers, focusing on building and maintaining the next generation of Google platforms.
This is an excellent opportunity for someone passionate about hardware design and looking to make a significant impact at scale. You'll be working with cutting-edge technologies and protocols like PCIe, UCIe, DDR, AXI, and ARM processors. The role offers the chance to work on complex technical challenges while being part of a company known for its innovative culture and global impact.
As a Senior SoC and IP Design Engineer, you'll be at the forefront of developing the architecture that powers Google's extensive product portfolio. The position requires a blend of technical expertise, collaborative skills, and innovative thinking to create efficient and powerful silicon solutions that meet Google's high standards of performance and reliability.
Responsibilities For Senior SoC and IP Design Engineer
- Define the SoC/block level design document such as interface protocol, block diagram, transaction flow, pipeline etc.
- Perform Register-Transfer Level (RTL) development (e.g., coding and debug in Verilog, SystemVerilog), function/performance simulation debug and Lint/CDC/FV/UPF checks
- Participate in synthesis, timing/power closure and ASIC silicon bring-up
- Participate in test plan and coverage analysis of the block and SoC level verification
- Communicate and work with multi-disciplined and multi-site teams
Requirements For Senior SoC and IP Design Engineer
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field, or equivalent practical experience
- 5 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog
- Experience with logic synthesis techniques to optimize RTL code, performance and power as well as low-power design techniques
- Experience in logic design and debug with Design Verification (DV)
- Experience with design sign-off and quality tools (e.g., Lint, CDC, etc.)
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