Senior SoC and IP Design Engineer
Description For Senior SoC and IP Design Engineer
Google Cloud is seeking a Senior SoC and IP Design Engineer to join their Technical Infrastructure team. This role is crucial in developing custom silicon solutions that power Google's direct-to-consumer products. As part of the team, you'll be working on cutting-edge hardware architecture that supports Google's vast product portfolio.
The position offers an opportunity to work with state-of-the-art technology in silicon design, focusing on System-on-Chip (SoC) and IP development. You'll be involved in the entire design process, from documentation and RTL development to verification and silicon bring-up. The role requires expertise in digital logic design, verification, and optimization techniques.
Working at Google means being part of a diverse team that pushes boundaries and innovates continuously. You'll contribute to products used by millions of users worldwide, ensuring optimal performance and efficiency. The Technical Infrastructure team is proud to be the "engineers' engineers," taking on complex challenges and building next-generation platforms.
The ideal candidate will have strong experience in RTL design, verification, and low-power design techniques. Knowledge of various protocols (PCIe, UCIe, DDR, AXI) and ARM processors is valuable. You'll work in a collaborative environment, communicating with multi-disciplined and multi-site teams to deliver high-quality solutions.
This role offers the opportunity to shape the future of Google's hardware experiences, working with cutting-edge technology and some of the industry's best engineers. You'll be part of a team that values innovation, technical excellence, and collaborative problem-solving. The position is based in Tel Aviv, Israel, where you'll have access to Google's world-class facilities and resources.
Responsibilities For Senior SoC and IP Design Engineer
- Define the SoC/block level design document such as interface protocol, block diagram, transaction flow, pipeline etc.
- Perform Register-Transfer Level (RTL) development (e.g., coding and debug in Verilog, SystemVerilog), function/performance simulation debug and Lint/CDC/FV/UPF checks
- Participate in synthesis, timing/power closure and ASIC silicon bring-up
- Participate in test plan and coverage analysis of the block and SoC level verification
- Communicate and work with multi-disciplined and multi-site teams
Requirements For Senior SoC and IP Design Engineer
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field, or equivalent practical experience
- 5 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog
- Experience with logic synthesis techniques to optimize RTL code, performance and power as well as low-power design techniques
- Experience in logic design and debug with Design Verification (DV)
- Experience with design sign-off and quality tools (e.g., Lint, CDC, etc.)
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