Senior SoC and IP Design Engineer
Description For Senior SoC and IP Design Engineer
Google is seeking a Senior SoC and IP Design Engineer to join their Technical Infrastructure team, focusing on developing custom silicon solutions that power Google's direct-to-consumer products. This role is crucial in shaping the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a Senior SoC and IP Design Engineer, you'll be working with cutting-edge technology in digital logic design, RTL development, and system-on-chip architecture. You'll be responsible for defining block-level design documents, performing RTL development, and participating in various aspects of the chip development process from synthesis to silicon bring-up.
The ideal candidate should have strong experience in digital logic design principles, RTL design concepts, and verification methodologies. Knowledge of high-performance and low-power design techniques is highly valued, along with expertise in protocols like PCIe, UCIe, DDR, AXI, and ARM processors.
This position offers the opportunity to work with a diverse, multi-disciplined team that pushes boundaries in hardware development. You'll be part of the team that maintains Google's technical infrastructure, ensuring optimal performance and efficiency of Google's vast product portfolio. The role combines technical expertise with collaborative teamwork, making it perfect for someone who wants to impact millions of users worldwide through hardware innovation.
Working at Google means joining a company committed to equal opportunity and fostering a culture of belonging. You'll be part of an organization that values diversity and provides comprehensive benefits while working on projects that shape the future of technology.
Responsibilities For Senior SoC and IP Design Engineer
- Define the SoC/block level design document such as interface protocol, block diagram, transaction flow, pipeline etc.
- Perform Register-Transfer Level (RTL) development (e.g., coding and debug in Verilog, SystemVerilog), function/performance simulation debug and Lint/CDC/FV/UPF checks
- Participate in synthesis, timing/power closure and ASIC silicon bring-up
- Participate in test plan and coverage analysis of the block and SoC level verification
- Communicate and work with multi-disciplined and multi-site teams
Requirements For Senior SoC and IP Design Engineer
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field, or equivalent practical experience
- 5 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog
- Experience with logic synthesis techniques to optimize RTL code, performance and power as well as low-power design techniques
- Experience in logic design and debug with Design Verification (DV)
- Experience with design sign-off and quality tools (e.g., Lint, CDC, etc.)
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