Senior Staff Chip Package Signal Integrity Engineer
Description For Senior Staff Chip Package Signal Integrity Engineer
Google is seeking a Senior Staff Chip Package Signal Integrity Engineer to join their hardware team. This role offers an exciting opportunity to work on cutting-edge silicon solutions that power Google's direct-to-consumer products. The position requires extensive experience in chip design and development, with a focus on high-speed serdes interfaces and 2.5D/3D package technology.
The role involves leading complex hardware projects, working with cross-functional teams, and contributing to next-generation hardware experiences. You'll be responsible for analyzing end-to-end Signal Integrity and Power Integrity (SIPI) to ensure optimal performance in High Performance Computing (HPC) applications. The position requires collaboration with various teams to define SI/PI design goals and trade-offs for chip/package design closure.
The ideal candidate will have at least 10 years of experience in silicon-based ICs and chips development, with a strong educational background in Electrical Engineering, Computer Engineering, or Computer Science. Experience with high-speed serdes IP evaluation, post-silicon validation, and 2.5D/3D package design is crucial.
Working at Google offers competitive compensation, including a base salary range of $221,000-$314,000, plus bonus, equity, and comprehensive benefits. You'll be part of a diverse team that pushes boundaries and develops custom silicon solutions, contributing to products used by millions worldwide. The role provides opportunities to shape the future of hardware experiences while working with industry-leading technologies and participating in influential working groups like IEEE P802.3dj.
This position combines technical leadership, innovative design work, and strategic planning, making it an excellent opportunity for experienced professionals looking to make a significant impact in hardware development at one of the world's leading technology companies.
Responsibilities For Senior Staff Chip Package Signal Integrity Engineer
- Lead the design of chips, packages, and systems for high speed serdes interface
- Establish and drive our roadmap of high speed serdes including Analog Front End (AFE) and Digital Signal Processor (DSP) requirements
- Validate post-silicon and qualification for new product introduction (NPI)
- Evaluate and integrate high-speed SerDes IPs
- Participate in IEEE P802.3dj working group
Requirements For Senior Staff Chip Package Signal Integrity Engineer
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience
- 10 years of experience with industry-standard tools, languages and methodologies relevant to the development of silicon-based ICs and chips
- Experience working cross functionally with chip top design, physical design, static timing analysis (STA), package, system, validation teams
- Experience in high speed serdes IP evaluation, post silicon validation, and debugging
- Experience with 2.5D/3D package design such as silicon interposer, silicon bridge, 3D die stacking
- Knowledge of channel design and sign off as well as serdes system modeling
- Knowledge of next generation serdes and package technology
Benefits For Senior Staff Chip Package Signal Integrity Engineer
- Bonus
- Equity
- Benefits package
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