Silicon Design Verification Engineer, TPU, Google Cloud

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Mid-Level Software Engineer
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Description For Silicon Design Verification Engineer, TPU, Google Cloud

Google is seeking a Silicon Design Verification Engineer for their TPU (Tensor Processing Unit) team within Google Cloud. This role is crucial in shaping the future of AI/ML hardware acceleration, working on cutting-edge TPU technology that powers Google's most demanding AI/ML applications. As part of a diverse team, you'll be developing custom silicon solutions and verifying complex digital designs, specifically focusing on TPU architecture and its integration within AI/ML-driven systems.

The position involves owning the full verification life cycle, from planning to coverage closure, with a strong emphasis on meeting AI/ML performance and accuracy goals. You'll be responsible for building constrained-random verification environments to ensure reliability of AI/ML workloads on TPU hardware. The role requires close collaboration with design and verification engineers on active projects.

Working in the Technical Infrastructure team, you'll be part of the backbone that keeps Google's vast product portfolio running. The team takes pride in being the engineers' engineers, maintaining data centers, and building next-generation Google platforms. This role offers an opportunity to contribute to the innovation behind products used by millions worldwide, leveraging your design and verification expertise in a cutting-edge technology environment.

The ideal candidate should have strong experience with verification methodologies, particularly UVM, and a solid background in IP design verification. Knowledge of SystemVerilog and functional coverage is essential. The role offers an opportunity to work with state-of-the-art AI/ML hardware acceleration technology while being part of Google's mission to advance computing capabilities.

Last updated a day ago

Responsibilities For Silicon Design Verification Engineer, TPU, Google Cloud

  • Plan the verification of digital design blocks and interact with design engineers to identify important verification scenarios
  • Identify and write all types of coverage measures for stimulus and corner-cases
  • Debug tests with design engineers to deliver functionally correct design blocks
  • Measure to identify verification holes and to show progress towards tape-out
  • Create a constrained-random verification environment using SystemVerilog and Universal verification methodology (UVM)

Requirements For Silicon Design Verification Engineer, TPU, Google Cloud

  • Bachelor's degree in Electrical Engineering or equivalent practical experience
  • 4 years of experience with verification methodology such as Universal verification methodology (UVM)
  • 2 years of experience in the verification of IP designs such as IP, SoC, vector CPUs, etc.
  • Experience with SystemVerilog, SVA, and functional coverage
  • Master's degree in Electrical Engineering or a related field (preferred)
  • Experience with industry-standard simulators, revision control systems, and regression systems (preferred)
  • Experience with the full verification life cycle (preferred)
  • Experience in Artificial Intelligence/Machine Learning (AI/ML) Accelerators or vector processing units (preferred)
  • Excellent problem solving and communication skills (preferred)

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