Silicon Design Verification Engineer, TPU, Google Cloud

Google is a global technology leader that develops innovative products and services used by billions of people worldwide.
Hardware
Mid-Level Software Engineer
In-Person
5,000+ Employees
4+ years of experience
AI

Description For Silicon Design Verification Engineer, TPU, Google Cloud

Google is seeking a Silicon Design Verification Engineer for their TPU (Tensor Processing Unit) team within Google Cloud. This role is crucial in shaping the future of AI/ML hardware acceleration, working on cutting-edge TPU technology that powers Google's most demanding AI/ML applications. The position involves being part of a diverse team developing custom silicon solutions for Google's TPU infrastructure. The engineer will own the full verification life cycle, from planning to coverage closure, with a focus on meeting AI/ML performance targets. They will build robust verification environments for TPU hardware and collaborate closely with design teams. The role is part of the Technical Infrastructure team, which is fundamental to keeping Google's services running efficiently. The ideal candidate should have strong experience in verification methodologies, SystemVerilog, and IP design verification, with a preference for AI/ML accelerator experience. This position offers the opportunity to work on technology that impacts millions of users worldwide while being at the forefront of AI hardware development.

Last updated 2 months ago

Responsibilities For Silicon Design Verification Engineer, TPU, Google Cloud

  • Plan the verification of digital design blocks and interact with design engineers to identify important verification scenarios
  • Identify and write all types of coverage measures for stimulus and corner-cases
  • Debug tests with design engineers to deliver functionally correct design blocks
  • Measure to identify verification holes and to show progress towards tape-out
  • Create a constrained-random verification environment using SystemVerilog and Universal verification methodology (UVM)

Requirements For Silicon Design Verification Engineer, TPU, Google Cloud

  • Bachelor's degree in Electrical Engineering or equivalent practical experience
  • 4 years of experience with verification methodology such as Universal verification methodology (UVM)
  • 2 years of experience in the verification of IP designs such as IP, SoC, vector CPUs, etc.
  • Experience with SystemVerilog, SVA, and functional coverage

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